From ffb7a2d7542bac4a33653e47e65b43b91a8eb8e0 Mon Sep 17 00:00:00 2001 From: Deepak Katragadda Date: Mon, 18 Apr 2016 17:22:22 -0700 Subject: [PATCH] clk: msm: clock-gcc-cobalt: Add clock reset support for additional clocks Add the BCR register for the gcc_ufs_axi_clk and gcc_blsp1/2_ahb_clk clocks. CRs-Fixed: 1005036 Change-Id: I8cd2403bed66141c99ccf8b9c57e59b936c1d90e Signed-off-by: Deepak Katragadda --- drivers/clk/msm/clock-gcc-cobalt.c | 3 +++ include/dt-bindings/clock/msm-clocks-hwio-cobalt.h | 3 +++ 2 files changed, 6 insertions(+) diff --git a/drivers/clk/msm/clock-gcc-cobalt.c b/drivers/clk/msm/clock-gcc-cobalt.c index 88d77977235d..1cbd40fa4ffc 100644 --- a/drivers/clk/msm/clock-gcc-cobalt.c +++ b/drivers/clk/msm/clock-gcc-cobalt.c @@ -1168,6 +1168,7 @@ static struct branch_clk gcc_bimc_mss_q6_axi_clk = { static struct local_vote_clk gcc_blsp1_ahb_clk = { .cbcr_reg = GCC_BLSP1_AHB_CBCR, + .bcr_reg = GCC_BLSP1_BCR, .vote_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE, .en_mask = BIT(17), .base = &virt_base, @@ -1360,6 +1361,7 @@ static struct branch_clk gcc_blsp1_uart3_apps_clk = { static struct local_vote_clk gcc_blsp2_ahb_clk = { .cbcr_reg = GCC_BLSP2_AHB_CBCR, + .bcr_reg = GCC_BLSP2_BCR, .vote_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE, .en_mask = BIT(15), .base = &virt_base, @@ -1958,6 +1960,7 @@ static struct branch_clk gcc_ufs_ahb_clk = { static struct branch_clk gcc_ufs_axi_clk = { .cbcr_reg = GCC_UFS_AXI_CBCR, + .bcr_reg = GCC_UFS_BCR, .has_sibling = 0, .base = &virt_base, .c = { diff --git a/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h b/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h index 2c92246827b6..d637d123e714 100644 --- a/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h +++ b/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h @@ -125,6 +125,7 @@ #define GCC_AGGRE1_USB3_AXI_CBCR 0x82024 #define GCC_BIMC_MSS_Q6_AXI_CBCR 0x4401C #define GCC_BLSP1_AHB_CBCR 0x17004 +#define GCC_BLSP1_BCR 0x17000 #define GCC_BLSP1_QUP1_SPI_APPS_CBCR 0x19004 #define GCC_BLSP1_QUP1_I2C_APPS_CBCR 0x19008 #define GCC_BLSP1_QUP2_SPI_APPS_CBCR 0x1B004 @@ -141,6 +142,7 @@ #define GCC_BLSP1_UART2_APPS_CBCR 0x1C004 #define GCC_BLSP1_UART3_APPS_CBCR 0x1E004 #define GCC_BLSP2_AHB_CBCR 0x25004 +#define GCC_BLSP2_BCR 0x25000 #define GCC_BLSP2_QUP1_SPI_APPS_CBCR 0x26004 #define GCC_BLSP2_QUP1_I2C_APPS_CBCR 0x26008 #define GCC_BLSP2_QUP2_I2C_APPS_CBCR 0x28008 @@ -195,6 +197,7 @@ #define GCC_TSIF_AHB_CBCR 0x36004 #define GCC_TSIF_REF_CBCR 0x36008 #define GCC_UFS_AXI_CBCR 0x75008 +#define GCC_UFS_BCR 0x75000 #define GCC_UFS_AHB_CBCR 0x7500C #define GCC_UFS_TX_SYMBOL_0_CBCR 0x75010 #define GCC_UFS_RX_SYMBOL_0_CBCR 0x75014