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9 commits

Author SHA1 Message Date
Maulik Shah
9a56229f15 lpm-levels: Remove kfree for memory allocated with devm_kzalloc
Do not use kfree for memory allocated with devm_kzalloc during
failures as device memory will get freed in device release.

Change-Id: I6c4d3f8ed55ab02e3e70a1fe65452a8817c8b64e
Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
2018-05-11 11:40:52 +05:30
Mahesh Sivasubramanian
5f3b521525 drivers: cpuidle: lpm-levels: Fix untrusted pointer dereference.
The list_for_each macro was not used correctly, where the intermediate
variable would be LIST_POISON, resulting in a untrusted pointer
dereference. Switch to using list_for_each_entry_safe to for safe
removal of a list entry.

Change-Id: I0e0fd5dd9f251b5093d6e9d6335387512ec59249
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
2018-01-10 12:31:28 +05:30
Raju P.L.S.S.S.N
46112a9d4a lpm-levels: Change _WARN_printf to pr_err when residency < 0
Change _WARN_printf to pr_err as former prints stack and
register dump in logs which is not necessary.

Change-Id: Ib0323014017818668a4a634e463f751fd5e9d24a
Signed-off-by: Raju P.L.S.S.S.N <rplsssn@codeaurora.org>
2016-10-22 22:40:42 -07:00
Raju P.L.S.S.S.N
201164f28b lpm-levels: Compute minimum residencies for LPM levels
Minimum residency of current level is maximum residency of previous
level + 1. If none of the previous levels are enabled, minimum
residency of currenct level is time_overhead of current level.

Minimum residencies are used for New LPM level selection using
prediction logic.

Change-Id: I5e69a847d78d14ecbb7caeac383287a1897f7ce8
Signed-off-by: Raju P.L.S.S.S.N <rplsssn@codeaurora.org>
2016-10-03 10:01:18 -06:00
Raju P.L.S.S.S.N
7aef3b1f9b lpm-levels: Fix low power mode selection
The low power mode selection logic has problems while
selecting best mode both in cpu and cluster selection.
When latency requirement is not met, the level selection
loop breaks without selecting another possible shallow
power mode that meets both latency and residency
requirements. The residencies are initialized to ~0
(0xFFFFFFFF) when a particular mode is disabled in idle
context. This results in wrong selection of shallower
mode in suspend context instead of selecting best possible
deepest low power mode (assuming the mode is enabled in
suspend context but disabled in idle context). This can
have impact on power.

The change addresses this by selecting a possible
shallower power mode that can meet the latency criteria.
It also initializes the residencies to 0 when a mode is
not allowed in idle context. This results in selection
of deepest low power mode in suspend context and
saves power.

Change-Id: Iae8b6ad74ef0f28d9c542315745577b1a5924664
Signed-off-by: Raju P.L.S.S.S.N <rplsssn@codeaurora.org>
2016-10-03 10:00:32 -06:00
Mahesh Sivasubramanian
0fb5a62a22 lpm-levels: Use residency instead of power and energy values
The driver looks through all the enabled modes and does energy
calculation runtime before it selects a low power mode to enter.
With residency values, the cpu/cluster can choose the low power
mode as soon as it comes across the low power mode which meets
the residency constraint.

Change-Id: I71235c212b26c3688a8ac5426942f2b88b681d47
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
2016-10-03 09:58:54 -06:00
Srinivas Rao L
99d535fc95 cpuidle: lpm-levels: Add API to get low power mode latency
Add API to get latency for a low power mode with particular
affinity level and reset level. Reset level is level at which
only control logic power collpase happen or both control and
memory logic power collapse happen or Retention state.

The API returns the minum latency out of all clusters in the
particular affinity level and reset level if cluster name is
not passed or the latency of the specific cluster for which
the cluster name is passed.

Change-Id: I2facd9a1fa2dba7e7103d65544537799bd8ba518
Signed-off-by: Srinivas Rao L <lsrao@codeaurora.org>

Conflicts:
	arch/arm/boot/dts/qcom/mdm9607-pm.dtsi
	arch/arm/boot/dts/qcom/mdm9640-pm.dtsi
	arch/arm/boot/dts/qcom/mdmcalifornium-pm.dtsi
	arch/arm/boot/dts/qcom/msm8909-pm8909-pm.dtsi
	arch/arm/boot/dts/qcom/msm8909-pm8916-pm.dtsi
	arch/arm/boot/dts/qcom/msm8937-pm.dtsi
	arch/arm/boot/dts/qcom/msm8952-pm.dtsi
	arch/arm/boot/dts/qcom/msmgold-pm.dtsi
	arch/arm/boot/dts/qcom/msmtitanium-pm.dtsi
2016-03-23 21:22:09 -07:00
Archana Sathyakumar
bda3760199 lpm: Allow cpu to enter FPC from hypervisor
FPC using PSCI is entered from PSCI layer that is in Secure EL1.
Switching of EL layers incur additional latency, making FPC slower.
Issue wfi within hypervisor for cpu only sleep. This makes FPC much
faster than entering from PSCI layer.

Change-Id: Icf4c5f2484fdda79c991b842cb3a3185b638bfdb
Signed-off-by: Archana Sathyakumar <asathyak@codeaurora.org>
2016-03-23 21:17:31 -07:00
Mahesh Sivasubramanian
c184ee865f soc: qcom: idle: Snapshot of idle/sleep driver as of msm-3.18
This is a snapshot of the Sleep driver and realted functionality as of
e70ad0cd5efdd9dc91a77dcdac31d6132e1315c1 on msm-3.18 branch

Change-Id: I98fec26849898c5c66abbb1b094439780c23964d
2016-03-22 11:07:18 -07:00