As per emmc specification, device should be notified either with
power-off or sleep notification before turning off the Vcc.
Failing to do so might affect the device longevity.
In mmc driver initialization phase even before device probing
gets completed, Vcc is getting turned off without these notifications.
Since it can't send commands at this stage, So just ensure that Vcc
is not turned off till initialization gets completed.
Change-Id: I0bbf0077357d66c888147be40a0c5d312b9ce063
Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>
Don't clear io pad power switch setting when 3V support is faked.
This bit has to be cleared for allowing IO pad to switch to 3V when
Vccq is really configured to 3V. But in case of faking 3V where we
configure Vccq to 1.8V only, we shouldn't clear this bit.
Change-Id: Ib1a9a2eb7189e161e22c8baf588453b3f2632eb7
Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>
On Certain chipsets, SDR104 mode might be unstable causing CRC error on
the interface. So we need a workaround which would skip printing register
dumps on CRC errors and also downgrade bus speed mode to SDR50/DDR50 in
case of continuous CRC errors. This patch adds "qcom,sdr104-wa" property
to enable this workaround if required.
Change-Id: I626d8ef45a97e8e6558e7f20be496de1f5a2a438
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Add debug RAM to store few important mmc data structures
on first point of failure(like mmc_card, mmc_host, sdhci_host)
for debugging purpose, otherwise it will be overwritten as
BUG_ON is removed now.
Change-Id: Ia1388a77aeed60d4d49a63b8798d3a925a60ac2c
Signed-off-by: Sayali Lokhande <sayalil@codeaurora.org>
Check if the SDHC has ICE HCI support. If support is present,
enable the cryptoghrapic support inside SDHC.
Also ensure that it is re-enabled after SDHC is reset.
By default ICE HCI is disabled.
Change-Id: I43a65279088d70b415c396bc3e51e0e510bb7f9c
Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>
For SDCC version 5.0.0, MCI registers are
removed from SDCC interface and some registers
are moved to HC. This change is to support MCI
register removal for msmfalcon.
New compatible string "qcom,sdhci-msm-v5" is
added for msmfalcon to support this change.
Change-Id: I9a972c5656762385f11214fe22398cc14a996d29
Signed-off-by: Sayali Lokhande <sayalil@codeaurora.org>
For any commands, that are sent during tuning sequence
CRC errors are expected. But if SDHCI_NEEDS_RETUNING flag
is set, then it will recursively do the tuning and gets
stuck in tuning. Fix this by not allowing the re-tuning to
happen while it is already in tuning process.
Change-Id: I9cc39f03a01c34f2f5639d4c20776fd575c25231
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
There could be a case where after platform device (sdhci_msm)
suspend, (where external gpio to IRQ is configured for wakeup
in case of sdio) external gpioIRQ is raised before
system suspend is completed.
To solve this problem we use a flag to signal
sdhci_msm_suspend_noirq to abort suspend with -EBUSY signal.
Change-Id: I82617d5a02674af24d330601e41fb3c20278f672
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
By delaying the QoS vote removal, there is some improvement
in performance in single threaded use cases.
Change-Id: I80545486057c55c697b72b56d57e2ea47cff86b9
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
This adds external GPIO wakeup support to sdhci-msm driver
for sdio cards.
Change-Id: Ic3e280b975d293ea8adadadafecfa8115fe5f428
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
ICE init & reset can be synchronous now because ICE does not need
to go to secure side for any ICE configuration. This would simplify
interface and make call more efficient.
Change-Id: I7aa4e2d3ba3383d25758b21b8ae261a0220f35f9
Signed-off-by: Dinesh K Garg <dineshg@codeaurora.org>
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
[subhashj@codeaurora.org: fixed merge conflicts, dropped changes
to ICE and UFS driver as they are already present]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
As SDIO spec doesn't allow advertisement of 1.8v support, some SDIO
devices advertise support of only 3.0v even though they support 1.8v
as well.
sdhc3 host controller only supports 1.8v and rejects the initialization
of SDIO devices that advertise 3.0v support.
This change adds fake support for 3.0v to sdhc host controller.
This will allow initialization of SDIO devices that supports 1.8v but
advertise 3.0v support.
Change-Id: I5a98c54ad4998e6439f83081628c9c083e95bbf0
Signed-off-by: Pavan Anamula <pavana@codeaurora.org>
Add sysfs entries to allow getting the current status of
PM QoS voting and enable or disable voting.
Change-Id: If5b8e4b155090343112916c9c57a766bb2104e10
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
Add PM QoS voting mechanism to sdhci-msm driver for legacy
eMMC.
Two types of voting schemes are supported:
1) Vote for HW IRQ
2) Vote for a cpu group according to the request's designated cpu
Using PM QoS voting should benefit performance.
Change-Id: I5d2b71fc4eabfa5060f343634fbc7363f2ee1344
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
[subhashj@codeaurora.org: fixed merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Add PM QoS voting mechanism to sdhci-msm driver for command queueing.
Two types of voting schemes are supported:
1) Vote for HW IRQ
2) Vote for a cpu group according to the request's designated cpu
Using PM QoS voting should benefit performance.
Change-Id: I8a20653eeb6348d5b442c846708d92c8fb64a8e9
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
[subhashj@codeaurora.org: fixed trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Add the necessary device tree properties and parsing in the driver
to support PM QoS voting for IRQ and CPU groups for CMDQ / legacy modes.
Change-Id: I1a94978ca66823d2ce78ee230cf36b4ebb72e6d8
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
[subhashj@codeaurora.org: fixed trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
pm_qos is causing race conditions in CQ mode with
power management. Removing the feature in order to
allow power management.
Change-Id: I340cd784829f389f18df6bff664337aca0f3c867
Signed-off-by: Dov Levenglick <dovl@codeaurora.org>
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
The power on reset value of DDR_CONFIG register was fixed in
controller revision (major - 0x1 and minor > 0x49) to address
the default rclk delay value after characterization. The register
offset for this register was also changed starting from this
revision. Make necessary changes to account for this.
Change-Id: I4e4a87aebd24e5669b03a914c6e0f4b469f5ec7b
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
This is needed to scale up/down the ICE clock during runtime
as per the load on eMMC.
Change-Id: I60d06458767c817298783219caf767866e7bf12f
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
If eMMC is not a primary bootdevice, there isn't any point of probing
eMMC device hence disable the probing in such case.
Change-Id: I92fa8c2ef373fd8a9140dbfb41356684aaa28e4e
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
eMMC controller may have an Inline Crypto Engine (ICE) attached,
which can be used to encrypt/decrypt data going to/from eMMC.
This patch adds a new client driver sdhci-msm-ice.c which interacts
with ICE driver present in (drivers/crypto/msm/) and thus provides
an interface to the low-level SDHCI driver to do the data
encryption/decryption.
Change-Id: I6ac78072563f77c481425a5ec149ec46a9b0a80d
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
[subhashj@codeaurora.org: fixed trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
