UFS PA errors were observed during data read operation hence Hardware
programming guide have recommended setting QSERDES_RX1_UCDR_PI_CONTROLS
register to value 0x81 which will use CDR DIV4 in all bands and fastlock.
Change-Id: I456354b346aca7abfaa4839d538c5054c3e79fbf
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
With the current SIGDET value of 0x6E there
seems to be NOP timeouts seen frequently.
Hence, change the SIGDET value to 0x6C as per
updated Hardware Programming Guide.
Change-Id: I46426382033603c4727de6b0a485015eed690f34
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Some UFS devices violate T-HIBERN8_ENTER_TX time when moving Device
TX (Host RX) lane-1 from SLEEP to HIBERN8 at the end of burst.
M-PHY specification defines max value of 1000 ns for
T-HIBERN8_ENTER_TX but these devices drive DIF-N for 3432 ns. This can
cause the broken link situation after link starup.
This change fixes above issue by increasing host PHY's RX_MIN_HIBERN8_TIME
to 8us (we are giving some additional margin though device needs 3.432us).
Change-Id: I55cb0b718e2e429c0378d842d85a02ace44bf2ce
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
The post silicon validated settings for phy-qcom-ufs-qmp-v3
applies only to the latest 2-lane phy version, revert the changes
and keep the original settings for 1-lane phy version.
Change-Id: Icb04f6175b66fa46405e77d10fddf06b0051ee5f
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
It's useful to dump phy registers on failure to debug
link issues. Export a new ops for the ufs driver to invoke
during link failures.
Change-Id: Id3a9c9085375b783d97e7f2ffd3e11ec469aedb9
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
New version of phy-qcom-ufs-qmp-v3 supports 2 lanes,
this change adds the config table to enable 2 lanes.
Change-Id: Ie916e7090d3660711159b886c27ee3709891ef2b
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Adjust phy-qcom-ufs-qmp-v3 settings based on post silicon validation.
Change-Id: Ide0ca4714679bb576a8069bdd7720507074ccc47
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
phy-qcom-ufs-qmp-v3 supports SVS2 voltage scaling mode that
allows lowest power consumption in HS G1. The PHY must be put
in hibern8 state before configuring the PHY to enter SVS2 mode.
The voltage can be reduced after this to SVS2 level.
This change exposes an API that allows the UFS driver to
configure the PHY to enter SVS2 mode.
Change-Id: I2ef01d98603840289c436e14bf3df54a2ab9198b
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Incorporate the new phy calibration sequence that adds additional
registers and modifies certain calibration data for ufs-qmp-v3 phy.
Change-Id: Id0ac493420a4d076f99b9f0d31b479a50f6eafd2
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
This change updates the offsets and calibration values of the
ufs-qmp-v3 phy.
Change-Id: I443a857b7b6620a65acd14e3a805eea9c00fd61c
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org>
Add support for new QCOM UFS PHY that is used in
future platforms.
Change-Id: I53f162738668ae9f24f5edb9c42a17f947e68b40
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org>
[venkatg@codeaurora.org: resolved trivial merge conflict]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
