As the best clocksource is not selected till core boot completion,
only periodic tick timer works and it increases jiffies by one at
every tick updates. If interrupt is disabled more than one tick(10ms),
timer interrupts are missed and jiffies can't be updated at every
10ms and it can be behind the real time. So make it possible to select
the best clocksource right after arm arch timer initialization, so that
jiffies can be increased by multiple counts since then.
Change-Id: Id8c4e3ce9b9e44061fef7ad7e678ca1c27d84bb1
Signed-off-by: Se Wang (Patrick) Oh <sewango@codeaurora.org>
Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
As the best clocksource is not selected till core boot completion,
only periodic tick timer works and it increases jiffies by one at
every tick updates. If interrupt is disabled more than one tick(10ms),
timer interrupts are missed and jiffies can't be updated at every
10ms and it can be behind the real time. So add API to force re-
selection of the best clocksource among registered clocksources so
that the best clocksource can be selected whenever it is available.
Change-Id: I481de3cdf1df8f0e35ed10aee7ab3882bf7a35b3
Signed-off-by: Se Wang (Patrick) Oh <sewango@codeaurora.org>
Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
Core 6 (MPIDR:0x102) and core 7 (MPIDR:0x103) are not
present in SDM658, SDA658 variants; so make relevant
updates to disable the cpu and other device nodes for
them.
Change-Id: I4633a3c36d367cc4ed5bbca525087d3d1cb57421
Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org>
Add sub-device node to allow mba to be able to load in carveout
memory region for SDM630.
Change-Id: Id249ca6512732572b9dce8d59b2e2713caaa7f9e
Signed-off-by: Gaurav Kohli <gkohli@codeaurora.org>
Return immediately from idle enter if there is no mode
selected. Log idle exit as failure to enter LPM in the
events that cpu needs to be rescheduled for another task.
Change-Id: I25a444682a8f8c9060f426c03e2f183f86d2fa3a
Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
cti-lpass0 and cti-lpass1 are not accessible as few of clocks/regulators
are not enabled to trigger the LPASS CTI.This cause device crash on
triggering the LPASS CTI on sdm660.Thus lpass-cti's are removed as
they are not planned to support from HLOS.
Change-Id: I76f81086919ea38b6966106f8ee6141baee183d6
Signed-off-by: Saranya Chidura <schidura@codeaurora.org>
The source clock of MMPLL10 has better jitter specs for MCLK than GPLL0_DIV
clock, so update the same to obtain 24MHz clock.
Change-Id: I57a77a83a5028c85d82fda4af53732f0bfb263e7
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Add MBA carveout of size 2MB after ADSP region and a buffer
region of size 1 MB in sync with v3 memory map.
Change-Id: Iaab9c43310d9ee4764ac73367bff3a448ea1f4d4
Signed-off-by: Prakash Gupta <guptap@codeaurora.org>
In core_channel_cleanup function channel is moved to dummy xprt
without taking channel lock. This leads to race condition where
transport poniter is pointing to dummy but channel still belong
to old transport.
Channel is moved to dummy with channel lock.
CRs-Fixed: 2005731
Change-Id: I91903140c1bfa29d909847f318d1339bb717fffc
Signed-off-by: Dhoat Harpal <hdhoat@codeaurora.org>
PM660 controls SMB1351 by STAT_CHG pin when the parallel is enabled.
the polarity of SMB1351 should be active high, so add a property
in DTS to the polarity.
CRs-Fixed: 2015025
Change-Id: Idca4149c587e9588fce8ba757fa0b7bf0ca5614d
Signed-off-by: Yingwei Zhao <cyizhao@codeaurora.org>
