Add support for R63417 DDIC based truly 1080p video and
command mode panel on sdm660.
Change-Id: I4435dadcfa1164bace99fdd603020cdea5809030
Signed-off-by: Vishnuvardhan Prodduturi <vproddut@codeaurora.org>
WCN3990 target uses different bit filed for ce
gather support.
Populate valid src descriptor buffers and gather
flag for WCN3990 target.
CRs-Fixed: 1115328
Change-Id: Ia7e73bd3009823357bb7df06eddb4903efb47286
Signed-off-by: Govind Singh <govinds@codeaurora.org>
Signed-off-by: Sarada Prasanna Garnayak <sgarna@codeaurora.org>
Up-streamed driver uses NAPI in rx data path. Add napi
implementation in snoc layer.
CRs-Fixed: 1112504
Change-Id: I33d3405ee99233af474f8bc236c43898086f044c
Signed-off-by: Govind Singh <govinds@codeaurora.org>
Add WCN3990 wlan module startup, power up and power down
sequence. Register interrupt handler and tasklet for each
copy engine interrupt line.
Add WCN3990 bus layer private API to configure and flush
the Tx/Rx copy engine pipe.
CRs-Fixed: 1112504
Change-Id: I9f0e2f080c8c92d0db5df465d3e79de058451b28
Signed-off-by: Govind Singh <govinds@codeaurora.org>
Signed-off-by: Sarada Prasanna Garnayak <sgarna@codeaurora.org>
RF clock of wcn3990 follows SW_CTRL pin. Enable this configuration for
lower power with BT/FM use cases.
CRs-Fixed: 2000919
Change-Id: I547d27a1d22824fa39578b65fdfffa6ce52c00cf
Signed-off-by: Rupesh Tatiya <rtatiya@codeaurora.org>
As WSA881x registers fails to read sometimes on
sdm660 internal codec, use cache-always mode
to avoid speaker mute.
CRs-Fixed: 1117406
Change-Id: Idaa2b4f7e53ea8f333eca3c0dc5b8f415266efd7
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
As WSA881x registers fails to read sometimes on
sdm660 internal codec, use cache-always mode
to avoid speaker mute.
CRs-Fixed: 1117406
Change-Id: I9742af37c3e64efb46fc9b3cef616f685b7f01a8
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
On SDM660 internal codec variant, update sequences of
MSM based soundwire codec. Skip the registration of
soundwire master IRQ handler as it is causing
continuous suspend/resume of soundwire controller.
Change-Id: Ic33b50aedca5b82e514518eb4bf6ce99cdc722b6
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
A512 GPU has multiple frequency plan, for loading a
specific frequency plan add speed bin read capability
for A512 GPU.
Change-Id: Iff207c31bc50748a6caaa405608252b78133fd83
Signed-off-by: Deepak Kumar <dkumar@codeaurora.org>
WDSP is connected to SPI7 in sdm660. So change
SPI master to 7.
CRs-Fixed: 2000921
Change-Id: I07eeef3e0753d38dbb33e4a343122b2948d36d38
Signed-off-by: Yeleswarapu Nagaradhesh <nagaradh@codeaurora.org>
There is no need for this property. Remove it.
Change-Id: I656eb51f8b9690d0c1046d1c82d2575fae270a40
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Currently the parallel charging code is tightly coupled in the main charger
files. Update the design to separate parallel charging code. This
parallel charging code will implement few votables and interacts with
the main and parallel charger.
A brief discussion on important changes
Usb main psy
The new design introduces a charger type called USB-Main which exposes all
the properties required to implement parallel charging for the main
charger. These properties are implemented/supported
- CONSTANT_CHARGE_CURRENT_MAX, sets and gets the FCC of the main charger
- ICL_REDUCTION, indicates by how much the main charger should reduce
its ICL. The parallel charger would draw some portion of the ICL and
this implementation ensures that the main charger reduce its ICL in
order to not exceed the adapter limits.
- VOLTAGE_MAX, sets the float voltage of the battery, we continue to
raise float voltage for the parallel charger so that it operates as
current source.
- INPUT_CURRENT_SETTLED: indicates the AICL results.
- FCC_DELTA: indicates the value by which the main is correcting the
FCC. The main reduces FCC by few mA when in Jeita or Step
charging. This helps in determining the exact FCC which in turn
helps distribute it correctly.
Slave percent
The new file implements the sysfs entry for slave percent. When
thermal balancer updates it, it ends up calling fcc distribution
and also the icl distribution. Note that the icl distribution too
is dependent on the slave's fcc percent - in that it gives 10
percent point more to the main charger.
ICL
ICL needs to be distributed only in USBIN_USBIN configuration.
As noted above the ICL distribution is based on fcc distribution
aka slave_percent. The main charger is given 10% more ICL since it
caters to system load in addition to charging the battery. This is
similar to our traditional USBIN USBIN implementation where FCC was
distributed 50/50 while ICL was distributed 60/40 percent - the main
got 10% more of the ICL value.
Note that the ICL distribution is invoked when AICL settled current
changes, not when the ICL itself changes. The new code tracks the
aicl settled value and invokes the icl distribution when it changes.
It first requests the main charger to reduce its icl and then updates
the parallel's icl.
FCC Votable
The FCC votable is moved to the new file and is similar to its previous
implementation - It distributes FCC when ever the FCC value changes, the
slave_pct changes or parallel charger is enabled or disabled. If the main
charger is further modifying the FCC from what its registers were
configured, this FCC callback takes that in to account via the
FCC_DELTA property prior to distribution.
FV Votable
Like the FCC votable the FV votable is moved to the new file.
The code is similar as it was implemented in the main file where
it distributes FV when ever the FV value changes.
TAPER entry
The code that stepwise reduces slave's ICL as it enters taper mode
is moved to this file. So that it can correctly do this, the
charge type is tracked in its internal structure.
PL_DISABLE Votable
The PL_DISABLE too is moved to a new file. There are few implementation
changes here.
- Earlier the code used to run the same sequence while enabling and
disabling. This could create a situation where FCC/ICL is incorrectly
configured for a brief period. That has been corrected, in that
the enable configures in this order configures fv, distributes fcc,
enables parallel, distributes aicl. The disable does that in reverse
order of enable.
- Charger's presence would vote on enabling/disabling parallel charger.
This is no more required. Instead a vote from CHG_STATE_VOTER suffices
for when fast charging begins. The voters that enable/disable parallel
when typec is present or is in sink mode or when uUSB cable is
inserted are removed.
CHG_STATE_VOTER and TAPER_END_VOTER
A typical charge cycle enters fast charging, moves to taper charging and
finally goes to end of charging. Parallel charging needs to be
enabled while fast charging starts and needs to be kept enabled during
the portion of taper charging when parallel's FCC is above 500mA threshold.
Note that if charging starts from taper, we only want to run it so long
as the parallel's FCC stays higher than 500mA threshold.
CHG_STATE_VOTER votes to enable parallel charging when fast charging
or parallel charging is in progress. When charging stops (i.e. when its not
in fast or taper charging) CHG_STATE_VOTER votes to disable parallel
charging.
Also the TAPER_END_VOTER votes to disable parallel charging when
parallel's FCC share falls below 500mA. It continues to vote disable on
parallel charging until charging stops. At that point it votes to
enable parallel charging.
Between these two voters, parallel charger
- enables when fast charging starts and remains enabled as it
transitions to taper charge.
- is disabled once parallel's FCC falls below 500mA threshold and
remains disabled in taper charge until charging stops.
This makes it important that the battery psy provide correct psy
changes when it enters/exit FAST or TAPER type. The PMI chip and its
battery_psy implementation already guarantees that.
PL_TAPER_EARLY_BAD_VOTER
During some runs we see that parallel operates in taper mode. Given that
we sets its FV higher than main's FV, the parallel should never operate
in taper mode. This voter disables parallel charging if this happens.
This voter enables parallel charging when the main charger stops
charging.
Change-Id: If1676cd126d7eeace7c44cf8d819038d03433d7e
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
A512 GPU's quirk two-pass-wfi is fixed in HW and no need to
enable from SW.
Change-Id: I3aa4d4d9a8f9be778e217b730c557b2b3a40345c
Signed-off-by: Rajesh Kemisetti <rajeshk@codeaurora.org>
Allow process on application processor to be associated with a
process on DSP that has been spawned on bootup. This allows for
further RPC calls to be associated with the static process.
Change-Id: Id4b9f01ef47290bc885210bbf4da1796476ba85f
Acked-by: Ashwini Patil <aapatil@qti.qualcomm.com>
Signed-off-by: Sathish Ambley <sathishambley@codeaurora.org>
There is no advantage of tracking busy time counters per related
thread group. We need busy time across all groups for either a CPU
or a frequency domain. Hence maintain group busy time counters in
the runqueue itself. When CPU window is rolled over, the group busy
counters are also rolled over. This eliminates the overhead of
individual group's window_start maintenance.
As we are preallocating related thread group now, this patch saves
40 * nr_cpu_ids * (nr_grp - 1) bytes memory.
Change-Id: Ieaaccea483b377f54ea1761e6939ee23a78a5e9c
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
Add 274.29 MHz as a supported frequency for the csi RCGs on
MSM8998 v2.
Change-Id: I4b8186c88fb66da21a1313f51b1080ee24c4b90f
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
FG SRAM read/write APIs consist of peripheral/supporting
read/writes and the core interleaved_mem_access functions.
The current implementation retries only when the core functions
return an error and in case of a read, additionally when the beat
count changes. This works except if the peripheral/supporting
access fail, we do not even retry.
Introduce retries for all possible failures while reading/writing
a SRAM location.
Change-Id: I99ad9acae3ef0dbc3941094076f124d16099468c
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
In the SRAM masked write we read the register first, make
modification to the value and write it back. If the read fails
we bail out of the masked write function.
However there is a bug in the read api where the error code is
not properly returned. This causes the masked write to proceed
with a failed read and corruption ensues.
A similar bug is present in write api too where the error is not
returned correctly to the caller. Fix this.
Change-Id: Ic7651c5cb2e054a0b8b2dfe201463063ce9e167b
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
PD 3.0 version 1.1 includes a new Programmable Power Supply
type that can be sent as an Augmented Power Data Object in a
Source Capabilities message. Add sink-side support to request an
Augmented PDO which also includes specifying the source's output
output voltage and current. For userspace, overload the 'select_pdo'
sysfs attribute by allowing voltage (uV) and current (uA) to be
optionally written, with the following syntax:
echo <src cap id> <PDO> [<uV> <uA>] > select_pdo
Also rename the 'rdo' file to 'rdo_h' as it is already in human-
readable format, enhance it with APDO values, and make 'rdo' simply
spit out the hex value.
Change-Id: If861b0f8f2f04d06299f096ff52f1e1961c1daa9
Signed-off-by: Jack Pham <jackp@codeaurora.org>
Set maximum revision support for 3.0 when starting in
PE_SNK_STARTUP state. If the partner source only supports
2.0, the spec_rev will be downgraded when receiving the
first Source_Capabilities message in phy_msg_received().
Add a helper to check for SinkTxOk (i.e. Rp indicates 3A)
before initiating an AMS sequence from PE_SNK_READY.
Currently such sequences are limited to power re-negotiation,
sink-initiated data/power role swap, and initiating VDMs.
Change-Id: I781c8826ded6e407297d50579d90bfd24783b164
Signed-off-by: Jack Pham <jackp@codeaurora.org>
To allow for future support of PD specification revision
3.0, update the PD_MSG_HDR macro to specify the revision
bits in each outgoing message header. The revision itself
will be kept in the struct pdphy. Also export a PD PHY
function to update the same for the auto-GoodCRC responses.
For now, only Rev 2.0 is supported.
Change-Id: I36e1b85f2e67597bd4fa8f0dd277374553451949
Signed-off-by: Jack Pham <jackp@codeaurora.org>
Maximum hardware supported speed flag limits the maximum speed
of the usb controller to high or super. Adding this additional
flag as maximum_speed flag can be changed from different sources
such as power delivery stack.
Change-Id: I18f414e822b5525fe848a48384fac102cdae7b03
Signed-off-by: Vamsi Krishna Samavedam <vskrishn@codeaurora.org>
Enable FW rejuvenate feature so that WLAN FW
can rejuvenate by default without changing the
configuration from debugfs.
CRs-Fixed: 2000561
Change-Id: Ic9b0524311c08bf3b99f43881054c23967734e5c
Signed-off-by: Yuanyuan Liu <yuanliu@codeaurora.org>
enable_fw_log is renamed to fw_log_mode and changed
from boolean type to uint8_t, so that it can support
multiple log mode.
CRs-Fixed: 1116983
Change-Id: I9d4af7cd2c857b62f434d968f51af76121006907
Signed-off-by: Yuanyuan Liu <yuanliu@codeaurora.org>
SDHC v5.0 onwards the ICE reset register offset got updated.
Update the register offset based on the SDHC version.
Change-Id: I9c1250460cddf72837446b54fe03e3c52f11b234
Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>
Check if the SDHC has ICE HCI support. If support is present,
enable the cryptoghrapic support inside SDHC.
Also ensure that it is re-enabled after SDHC is reset.
By default ICE HCI is disabled.
Change-Id: I43a65279088d70b415c396bc3e51e0e510bb7f9c
Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>
