Initialize coresight at boot time so that it is available to be
configured before the first open of /dev/kgsl-3d0 to get GPU
scan dumps during initial power up.
Change-Id: Ic0dedbadbda251f12855895cc0aa53852f79a8b8
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Add a quirk to mask out the RB 1-3 activity signals in the hang
detection logic. Set this quirk in the devicetree for 8996v2 and
v3.
CRs-Fixed: 978849
Change-Id: I63073b5973644453e775b41a9361de55d7933a07
Signed-off-by: Shrenuj Bansal <shrenujb@codeaurora.org>
During the initialization sequence, submit a set of important
packets to the GPU in order to pre-load the I-cache with the
critical ucode instructions.
CRs-Fixed: 978777
Change-Id: Ic6a17b24d8c3aa383af8e25cf9ef771459d65796
Signed-off-by: Shrenuj Bansal <shrenujb@codeaurora.org>
Some platforms support multiple GPU clock plans based on the speed
bin in the efuse. Specify the wake up frequency of each speed bin
individually to wake the gpu at the correct powerlevel.
CRs-Fixed: 967494
Change-Id: I9890b8a710d7055c30f9ae7612b092af8fa8a9f5
Signed-off-by: Suman Tatiraju <sumant@codeaurora.org>
adreno_spin_idle spins for a timeout checking for gpu to idle.
Sometimes due to race conditions the timeout can occur before the
loop is executed. Change the logic to a do-while loop and add an
extra idle check after the timeout before returning failure.
CRs-Fixed: 978122
Change-Id: Idb92a0180dd8cc3e662b1ccf44d69e4bbafb29f1
Signed-off-by: Suman Tatiraju <sumant@codeaurora.org>
On 5XX targets we need to program the bit of the highest DDR bank
into a number of registers, one of which is protected which would
cause problems if the user mode driver tried to write to it.
Specify the high bank bit in the device tree files, set the
problematic register in the kernel and then pass the value up to
the user mode driver as a property and let them program the
other registers. This makes the device tree the authoratative
source of the high bit value which is exactly how it should be.
If the value isn't specified by the device tree for whatever reason
return an error for the property request - that will give the UMD
a clue that the value wasn't specified and they should just set a
default.
CRs-Fixed: 970272
Change-Id: Ic0dedbad830321329b74da7fa3e172fdaf765c4d
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
This change set default value for uninitialized variables,
to address errors related to them.
Change-Id: Idd306cafa4dfca322945ea8398e0c4d6c18d6ff6
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
Ensure that all the logs that can be triggered from the
interrupt handler are rate limited.
CRs-Fixed: 971145
Change-Id: I9fe4a6b28be0dc6299467fb8402bef3694aeac76
Signed-off-by: Carter Cooper <ccooper@codeaurora.org>
The current MMU code assumes a binary state - either there is a
IOMMU or there isn't. This precludes other memory models and
makes for a lot of inherent IOMMU knowledge in the generic MMU
code and the rest of the driver. Reorganize and cleanup the
MMU and IOMMU code:
* Add a Kconfig boolean dependent on ARM and/or MSM SMMU support.
* Make "nommu" mode an actual MMU subtype and figure out available
MMU subtypes at probe time.
* Move IOMMU device tree parsing to the IOMMU code.
* Move the MMU subtype private structures into struct kgsl_mmu.
* Move adreno_iommu specific functions out of other generic
adreno code.
* Move A4XX specific preemption code out of the ringbuffer code.
CRs-Fixed: 970264
Change-Id: Ic0dedbad1293a1d129b7c4ed1105d684ca84d97f
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
There can only be one module_init() function per module. Move all
three driver register calls into the same initialization function. The
ordering should still work correctly.
Change-Id: Ic0dedbadf7c69221a836ba3bbba362d0660f1f0f
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Add a helper macro to convert an adreno_device pointer to a
struct kgsl_device pointer. This is mostly syntatic sugar
but it makes the code a bit cleaner and it abstracts a bit of
the ugliness away.
Change-Id: Ic0dedbadd97bda3316a58514a5a64757bd4154c7
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
CP_CACHE_FLUSH interrupts can storm on very rare occasions.
Check for this interrupt storm and do nothing when it occurs
rather than thrashing the CPU which can occasionally bring the
system down.
Change-Id: I0528ad4fec43abfaeeba1499d0b0e51e14b09f0d
Signed-off-by: Carter Cooper <ccooper@codeaurora.org>
Global pagetable entries are exclusively for IOMMU and per-process
pagetables. Move all the code out of the generic driver and into
the IOMMU driver and clean up a bunch of stuff along the way.
Change-Id: Ic0dedbadbb368bb2a289ba4393f729d7e6066a17
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Limits management can force clock throttling which results in incorrect
busy percentage calculation. We need to account for that in DCVS.
Change-Id: Iaa17a7f7d661ab9966597f7710374d5b2e00d514
Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
Make the various timeout values HZ agnostic by using the proper
macros and values instead.
Change-Id: I708cd491f593782f0172cd7d2cca058cd41044a5
Signed-off-by: Suman Tatiraju <sumant@codeaurora.org>
Add ISENSE based limit management, provide interfaces to GPMU
and hardware LLM and BCL subsystems.
Change-Id: Ic0419509bdc6d4d9d478277cc90ae75dc527ca66
Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
Setting the GPU to 64bit when rest of world is in 32bit can
make the GPU misbehave. Hence, check the kernel configuration
before actually moving the GPU to 64bit mode.
Change-Id: Ie4cf6c2d4fdfa978287c86812bdce4bf8c56ef5f
Signed-off-by: Rajesh Kemisetti <rajeshk@codeaurora.org>
Make several changes to build the GPU driver for 4.4:
- Rename CONFIG_MSM to CONFIG_QCOM where applicable
- Add msm_kgsl.h to the Kbuild exports
- Remove linux/coresight_of.h (as it has been merged into
coresight.h) and remove the .owner member of the
coresight_desc struct.
- Use the new location for the sync.h file (in staging)
- Remove an unused sync function
- Move oneshot_sync.h inside of #ifdef wrappers
Signed-off-by: Jordan Crouse <jcrouse@codeauorora.org>
Snapshot of the Qualcom Adreno GPU driver (KGSL) as of msm-3.18 commit
commit e70ad0cd5efd ("Promotion of kernel.lnx.3.18-151201.").
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
