There is ref count mismatch in number of enable/disable calls for
regulators with low power mode allowed flag which is resulting in
random system crashes. This change makes sure number of enable/disable
calls are same.
Change-Id: I0c1906df8c3a83e8740412c272179d3d9c514c0e
Signed-off-by: Rashi Bindra <rbindra@codeaurora.org>
Remove wait for vsync in display commit if both PCC and DDIC
need to update for external backlight feature.
Change-Id: I57aeb48acba24e0ca3fff21b1117e48fe452028b
Signed-off-by: Xu Yang <yangxu@codeaurora.org>
If there is any failure while registering a DBA client with MDSS
driver, then remove the client from device client list first and
then free the client. Otherwise driver might crash when
traversing the device client list in later stage, because of an
uninitialized entry in the list.
Change-Id: I60666f4c3dea5c7ea7b7c77bcb14b080ee25b54d
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
In case sync trigger is enabled, then DCS commands are only
sent for both the DSI controller when transfer call for the
second DSI controller happens. So in that case do not print
error log for the first controller if DCS command is not sent.
Change-Id: I5c302f55f15735970cd5f6c8d0b31c55b447433f
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
For some platforms, after turning on the VREG for ADV7533 bridge
chip, need to sleep some period of time before doing any
I2C transactions with the bridge chip.
Change-Id: I6f7c45f3561f996507613a7a6eb0bcd8922caed5
Signed-off-by: Yunyun Cao <yunyunc@codeaurora.org>
Enable TE irq for the panel when there is a pingpong timeout.
Wait for TE to come for five vsync cycles before starting the
recovery for panel dead. If the TE comes from the panel during
the wait, call panic for pingpong timeout.
Change-Id: I88d06562e3e19880bb327b5f347ed79057f0e8c3
Signed-off-by: Ashish Garg <ashigarg@codeaurora.org>
Signed-off-by: Vishnuvardhan Prodduturi <vproddut@codeaurora.org>
With DSC enabled in the panel interface, the horizontal pixel count is
smaller than the panel width due to the compression. Correcting the
time_of_line and total_line calculation by calling the proper macro.
CRs-Fixed: 2048339
Change-Id: I36c1b9d30d5a440dfef4b4638f4f3ebf807782c8
Signed-off-by: Benjamin Chan <bkchan@codeaurora.org>
Disable AVR as dynamic fps is enabled for msm8998.
Change-Id: I4d96984c45de83868f2ea4d324a598edf6d30e94
Signed-off-by: Sachin Bhayare <sachin.bhayare@codeaurora.org>
During atomic commit on a writeback panel, there is a possibility
of deferencing a NULL pointer if the configuration changes before
the commit. This change adds a NULL pointer check to avoid it.
Change-Id: I56d0efad40992b6f87c81e5eab93cf0f24f6f524
Signed-off-by: Rajkumar Subbiah <rsubbia@codeaurora.org>
For larger panel with longer vertical pixel count, it is possible that
bandwidth requirement is much higher during downscaling usecase. Current
bandwidth calculation for compression ratio adjustment only use 32-bit
and it is shown that overflow can happen, and is required to change to
use 64-bit variable as input and output.
CRs-Fixed: 2045602
Change-Id: I817e9d55fb6e24e686513327d00f7efd08ac717f
Signed-off-by: Benjamin Chan <bkchan@codeaurora.org>
There can be cases where MDP is resuming at default fps
and in between dfps update comes before unblank is completed.
This might result in mismatch in fps and blanking
settings in MDP and DSI. Hence avoid any fps update until
unblank is finished.
Change-Id: If4fed28b1d706f38c39fba06fa786eac6d9ed8c8
Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org>
Currently AD last_str is updated only inside pp_ad_calc_worker
thread which is trigged by backlight or ambient light changes.
If the number of screen refreshes is too small or user suspends the
device before it finishes the scheduled screen refreshes, last_str
will be different from the target strength for the current inputs.
And when device goes into idle power collapse mode and exits, AD
will switch to manual strength mode with last_str for two frames.
After that, AD will go back to auto strength mode with the target
strength. Since last_str and target strength may be different,
flickers will be seen every time AD mode switch happens.
This change fixes this above issue by reading the AD strength register
and updating the value to last_str when AD mode switches from manual
mode to auto strength mode.
Change-Id: If68f84a4781230afe21b58c73ff88e59e7e9d416
Signed-off-by: Ping Li <pingli@codeaurora.org>
In case of 180 degree panel flip using pan display for commit,
correct source and destination buffer rectangles as mixer swap
is no longer supported.
Change-Id: Ifd31732ace6ebefd865933b6be359374e4a9fa63
Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org>
Need consider both SINK and SOURCE max supported TMDS
clock. For the devices, if we set TMDS clock larger than
device caps, it could not display well. SINK max TMDS
clock could read from HDMI VSDB and HF-VSDB in EDID.
CRs-Fixed: 2035529
Change-Id: I1f31f2a05d0502367b877c4d324cbc131b2366d5
Signed-off-by: zhaoyuan <yzhao@codeaurora.org>
AVMUTE is applied when HDMI power off. However, when HDMI power
on, we just make AVMUTE false for CTA format. For non-CTA format,
AVMUTE is still applied, if we want to show premium data(highger
quality, such as enable deep color), HDMI could not display, just
black screen.
CRs-Fixed: 2033800
Change-Id: If0de6052e98cb9cfcf88ae21d8c19d39ae8abd14
Signed-off-by: zhaoyuan <yzhao@codeaurora.org>
Current driver checks if the address of start pointer is zero. But
in cases when start pointer is NULL this check will result in null
pointer dereferencing. This change adds an additioanl check on the
start pointer to avoid null pointer dereferencing.
CRs-fixed: 2035100
Change-Id: Ic86c9e73cd676cbf8680f5b7266ee3829f4ccbd2
Signed-off-by: Harsh Sahu <hsahu@codeaurora.org>
The AVR vtotal setup is done during ctl start. Since the slave
ctl is not yet setup, currently the master and slave controls
get flushed independently even though it is a split display
setup. Instead, just set a flag and then do the actual flush
as part of commit when the controls are properly setup.
Change-Id: I8eb1693c9a3a6404d28a82cab9a9f0ce58d1bb03
Signed-off-by: Rajkumar Subbiah <rsubbia@codeaurora.org>
Update mdss throttle clock status based on status of display.
Change-Id: Ife21df0c570240c075f039b8d49514bb323021da
Signed-off-by: Sachin Bhayare <sachin.bhayare@codeaurora.org>
Currently memcpy is copying from a bigger memory size to a smaller
memory size. This change corrects this issue by performing the
memcopy restricted to the smaller of the src or dest memory buffer.
CRs-fixed: 2028228
Change-Id: Ibbe5665083799a4262d3cfbb06f94f3e35e03748
Signed-off-by: Harsh Sahu <hsahu@codeaurora.org>
In bandwidth limit read function, 'buf' array
elements might be used uninitialized. Ensure
the array elements are initialized.
Change-Id: I210c73b14327436296a844fc5ebd47ccc02bf5fb
Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org>
For each input and output buffer given to mdss rotator, it is necessary
to check the range of the plane_count value against the MAX_PLANES
definition, in order to avoid any plane array out of bound access.
CRs-Fixed: 2028681
Change-Id: I117bf5daead17e5e97c62c6dc8e21d1fcc9d8e74
Signed-off-by: Benjamin Chan <bkchan@codeaurora.org>
For any given output buffer to the MDSS WFD, it is necessary to check
the range of the plane_count against the MAX_PLANES definition, in order
to avoid any out of bound access.
CRs-Fixed: 2028702
Change-Id: I4f1497a3a2e4ca2d30fc268e68cfdacc0d8539ea
Signed-off-by: Benjamin Chan <bkchan@codeaurora.org>
For non-atomic display commit that use pan_display, it is not possible
to use multi-rect feature from the DMA pipe. This fix is to reject any
multi-rect DMA pipe being used in the commit when all the non
multi-rect DMA pipes are not available.
CRs-Fixed: 2036486
Change-Id: I16722d62650807b5f46ca2bb544653f43a01edf1
Signed-off-by: Benjamin Chan <bkchan@codeaurora.org>
Display port main link control clock is enabled during UNBLANK ioctl call.
Due to some error reasons, UNBLANK ioctl call may early return without
enabling DP control clock. Later if any ioctl is called and tries
to access unclocked DP link registers, it will cause noc error.
Add a check to handle these ioctls only if DP is fully powered on.
Change-Id: Ie5a5707f708a0e39d21bf06b8e479b7b95249566
Signed-off-by: Narender Ankam <nankam@codeaurora.org>
LM flush is required in order to take DE/Scalar register changes
to take effect. Hence set the LM flush bit on the update.
Change-Id: I9b497b8109133d221d7009e9709149146f213c5e
Signed-off-by: Sravan Kumar D.V.N <sravank1@codeaurora.org>
