Update cpufreq table for sdm630 as per new cpu clock plan.
CRs-Fixed: 2008773
Change-Id: Ibaa5d3c2d1dbafd14b5e9bee382cd3980f89aa51
Signed-off-by: Tirupathi Reddy <tirupath@codeaurora.org>
Add device tree files for headset jacktype NO, for CDP
and RCM platforms of SDM630.
Change-Id: I297e6467ed47c51950ae527077c3d20cf738e0b6
Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org>
Fix default read vbif OT settings for mdss driver
in sdm630 and sdm660.
Change-Id: I9efbda397ffbf3552a165887d43e25a0426fd5b5
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
ICL change interrupt triggers whenever there is change in the
input ICL, in case of AICL restart(done as part of S/W base
pulsing) AICL starts from 500mA and ICL change gets triggered
for every 25mA ICL as part of AICL ramping.
ICL change handler generates a power_supply event on parallel
psys and thus causing parallel framework to re-split ICL for
every 25mA. Fix this by delaying power_supply event until AICL
settles.
Change-Id: I9270a99f536db4534e46764b2e053ff93b38cb54
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
Hardware autonomous INOV does adapter's output voltage
manipulation only based on the input limited state of main
charger. This works well with MID-MID parallel configuration
but with USBIN-USBIN parallel configuration parallel charger's
input limited state also plays role for INOV manipulations.
Thus disable hardware based autonomous INOV and add support
for software based INOV for USBIN-USBIN configuration.
Note that if authentication is disabled, the hw assumes QC3.0 and
if the autonomous bit is enabled, it issues increment/decrement pulses.
This happens even when QC3.0 has not been actually authenticated.
Change-Id: I397acb558c9ba3b6fc7d7b974d64459f278697fd
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
USBIN-USBIN parallel configuration can have either an internal current
sensing via main charger's BATFET or an external current sense resistor.
The FCC split between main and parallel charger differs based on current
sensing mode, add support to differentiate internal/external sensing and
the FCC split is done as follows:
- Internal Sensing: Main charger configure to full FCC
Parallel charger configured to 50% FCC.
- External sensing: Main charger configure to 50% FCC
Parallel charger configured to 50% FCC.
Change-Id: Ia0c6234ce6f62af460edd3c4f56e34810899b3e3
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
Via debugfs nodes, users have the option to read and write to
any PCIe register. To ensure clients do not access registers
outside the PCIe range, add checks to validate the offset clients
provide.
Change-Id: Ia35cd04c57f01c21a47962be596bca395b5ca247
Signed-off-by: Tony Truong <truong@codeaurora.org>
"icl_reduction_ua" is not updated to new slave ICL value after
ICL split, update the variable.
Change-Id: I944fddfda1aa2c359785d1a3155ac22ebe91fa65
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
In PM660 "QC authentication done" IRQ is a pulse and thus it
does not require workaround to disable this IRQ after authentication
completes. Add a workaround flag to enable this only for PMI8998.
Change-Id: I766219df38fc4954f5208d6db323b680e8e5fafd
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
In some cases it has been observed that after sending STARTXFER
command with USB GSI IN endpoint, USB controller is accessing zero
address resulting into bus error. This change captures USB GSI
operation sequence in debug buffer which may help to understand
race condition in terms of USB gadget events and USB GSI endpoint
operations.
Change-Id: Ia46877bb92ea0cc1d5f3712e5c70bb44232d5cfe
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
The hardware based threshold comparison requires thermal regulation to
be active. This is a problem for layouts which connect USBIN rather than
MID to the SMB138X since the thermal regulation will throttle the ICL in
the USBIN case.
Read the connector temperature ADC and compare against the thresholds
in software instead of enabling thermal regulation.
Change-Id: I9ecda675947fc6c82a8c8b67d0c9d930365ad02e
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
WCN3990 needs shadow register write operation support
for copy engine for regular operation in powersave mode.
Add support for copy engine shadow register write in
datapath tx for WCN3990
CRs-Fixed: 2008518
Change-Id: Ie90ff74984021fa47070e08b2fc53ad5da46cf35
Signed-off-by: Rakesh Pillai <pillair@codeaurora.org>
Modify the compatible string used for GFX LDO CPR for sdm630 to apply
sdm630 specific configuration.
CRs-Fixed: 2007621
Change-Id: I883a004c8731654f5752194d66c971a22ea723ef
Signed-off-by: Tirupathi Reddy <tirupath@codeaurora.org>
1. Add FRONT, BACK, AUX camera nodes.
2. Add CSID, CSIPHY,ISPIF, VFE, JPEG, CPP, nodes.
3. Add GPIO configuration in pinctrl.
4. Add support for upstream clock config.
5. Add sensor VAF to LDO8 with min vote of 2.8.
Change-Id: I49f1ec1941a080d85812309c7a8cce7302c49e25
Signed-off-by: Shankar Ravi <rshankar@codeaurora.org>
DCVS table specifies the low and high load interms
of mbs per sec. Clock frequency is derived from
this load alongwith cycles required per mb. For
starlord, the DCVS low load was incorrect which
made the decoder session to run in SVS instead
of SVS+. The change now fix it to proper load.
Change-Id: I46dd772aa349b94a75472477e24cabe80c088165
CRs-Fixed: 2007776
Signed-off-by: Vikash Garodia <vgarodia@codeaurora.org>
Update the proper number of bus frequency levels for SDM630 GPU.
Change-Id: Id00a47440dd766493a1de6da9cb0c218b1fa8eac
Signed-off-by: Rajesh Kemisetti <rajeshk@codeaurora.org>
