IPA allocates memory for Filtering and Routing tables
by the DMA memory allocation Linux APIs.
The code did not check the success of allocation
correctly. This change fixes the check.
CRs-fixed: 2014060
Change-Id: I95a170f19e3becfc2b90bf5931947c0637464257
Signed-off-by: Ghanim Fodi <gfodi@codeaurora.org>
Currently, mpm wakeup time is programmed in seconds
due to which there is a possibility that wakeup
happens later than the expected time. This patch
fixes the issue by programming the mpm wakeup time
in milliseconds.
CRs-Fixed: 2010001
Change-Id: I5c4905a0386e60ae54876f30d89f445fd06a161c
Signed-off-by: Mohit Aggarwal <maggarwa@codeaurora.org>
Add device nodes for dp_ctrl and dp_pll to bring up display port
on sdm630.
Change-Id: I14621a6e4d6273b56c1ad7639baa5e83c058fe63
Signed-off-by: Narender Ankam <nankam@codeaurora.org>
This reverts commit e355807417 ("ARM: dts:
msm: disable dynamic fps for nt35597 truly panel on sdm660").
Adding back dynamic fps support for nt35597 truly panel, since the
display split screen issue is root caused to be related to DSI BTA
operation.
Change-Id: If020eb482b3e53ea114365734663a8c14c37dc14
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
Alarmtimer will send suspend wake time in milliseconds
instead of seconds to minimize round off errors. Update
lpm-levels accordingly.
Change-Id: I58c780993ce35cda69cd963996f057d6e2265c6d
Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
Define structures for the copy engine misc registers
copy engine CMD halt, watermark source, watermark
destination, host IE ring.
This adds support to avoid the conditional compilation,
code optimization and dynamic configuration of the copy
engine register map for respective hardware bus interface.
Change-Id: I42b9c0ad0927b492e3b4f040ae7163456b161735
Signed-off-by: Sarada Prasanna Garnayak <sgarna@codeaurora.org>
Define a structure for the copy engine CTRL_1 register
source, destination and dmax ring. This adds support to
avoid the conditional compilation, code optimization and
dynamic configuration of the copy engine register map
for respective hardware bus interface.
Change-Id: Ic0a4190b0735fb5d905ea75ac71e8060260dde74
Signed-off-by: Sarada Prasanna Garnayak <sgarna@codeaurora.org>
Instead of defining the copy engine register map as a macro,
Define a structure for the copy engine register map to avoid
the conditional compilation, code optimization and dynamic
configuration of the copy engine register map for respective
hardware bus interface.
Change-Id: I799794ed85b83e342c2aab3d12b2876fc28d680b
Signed-off-by: Sarada Prasanna Garnayak <sgarna@codeaurora.org>
ath10k struct is bus opaque structure.
Remove bus structures from ath10k struct to make it
bus independent.
Change-Id: Ifb82e1fc4525c535e8a19f95bd4da006294be203
Signed-off-by: Govind Singh <govinds@codeaurora.org>
Update SDCC PM QOS latencies to allow l2-retention
state as per measured LPM latencies on SDM660 target.
Change-Id: Iac0a0473f78be90722ceb07db1f85ac6adb69911
Signed-off-by: Sayali Lokhande <sayalil@codeaurora.org>
On SDM660, for sdcc there are two msm-bus paths:
1. AGGNOC->SNOC->BIMC
2. CPU->CNOC->SDC_CFG
For SDCC DATA-FIFO or DPRAM, write clock is HCLK
and read clock is MCLK for TX transactions and
vice-versa for RX transactions.
As both HCLK and MCLK are being used for data
transfers ,we need to provide bus bandwidth vote
from CPU(id:1) to SDC_CFG(id:606) which will be
used for register access and data transfers.
By default on sdm660, we observed cnoc_clk at only
19.2MHz which is very less and hence affecting eMMC
performance (drop upto 50%) for read/writes.
This change is updating bus voting from CPU to CNOC
and helps improving eMMC performance.
Change-Id: I9e3dadf307444be464a42f4a518b44e3f6e98a75
Signed-off-by: Sayali Lokhande <sayalil@codeaurora.org>
A clk_get_rate in the clk_enable path would result in a BUG from sleeping
context, as clk_get_rate would hold a mutex when we have already acquired a
spinlock in the clk_enable.
Change-Id: I7b32292710bbea3565cdc51c79916fddc60f8bba
Signed-off-by: Taniya Das <tdas@codeaurora.org>
In the new SDM660 QRD devices, PM660 does not need the hardware
workround that cut-off voltage should be set to 3.7V, so delete
the qcom,fg-cutoff-voltage property.
CRs-Fixed: 2013279
Change-Id: Ica55128a2f426a668b0d43d04424e13672dd78fd
Signed-off-by: Yingwei Zhao <cyizhao@codeaurora.org>
This reverts commit 9f45a559c7 ("ARM: dts: msm:
add sb_4_tx_vi to support VI recording at msm8998")
It is unnecessary to support concurrency of VI sense
recording and speaker protection.
CRs-Fixed: 1113625
Change-Id: I13ee9fd2daed2ad55347c112eeb79a9bfe6495ba
Signed-off-by: Xiaojun Sang <xsang@codeaurora.org>
Add camera node including rear aux and front camera node, also
add corresponding eeprom actuator ois flash and torch node.
Change-Id: I84e3bfa11127ca7808491df728665f74c9222343
Signed-off-by: Pengfei Liu <pengfeiliu@codeaurora.org>
leds-qpnp-flash driver is not supported anymore. Remove it.
Change-Id: Ie2f570bad8171c460b8167f140d71c052ada2b17
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
When stack memory is provided to IPA HW as part of
descriptor it can lead to cache alignment issues.
Make changes to use heap memory whereever applicable.
Change-Id: I666f98cf2ec45a4743db0ab7bc6d2df821cce84a
Acked-by: Chaitanya Pratapa <cpratapa@qti.qualcomm.com>
Signed-off-by: Sridhar Ancha <sancha@codeaurora.org>
Signed-off-by: Utkarsh Saxena <usaxena@codeaurora.org>
If userspace provides a circular list to isp kenrel
driver through an ioctl, then dirver loops forever.
This way the task might hog the CPU in while loop.
To fix this issue, added a preset count to break
the loop after 100 iterations.
CRs-Fixed: 1064608
Change-Id: Ie896fd3da326e5e972266d8004baecf8681aea6d
Signed-off-by: VijayaKumar T M <vtmuni@codeaurora.org>
Signed-off-by: Lokesh Kumar Aakulu <lkumar@codeaurora.org>
