Currently the files in /sys/devices/soc0/ show no information about
DRA7. Few userspace programs do depend on this information to make SoC
specific support. So update logic to detect the relevant information and
provide to userspace.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
In omap2_common_pm_late_init suspend_set_ops was called to set common
suspend handling functions for all omap platforms. This created two
problems. First, these suspend ops were being set for all platforms,
regardless of whether or not suspend support has been integrated so in
the case of AM33XX, suspend to mem was presented as available but
failed every time. Second, some platforms will need to define a
completely separate set of suspend ops, such as AM33XX, due to
differences from previous omap platforms so there is no need to
always set the common omap ops.
This patch moves the suspend_set_ops call from omap2_common_pm_late_init
into a separate function that then gets called in the omap*_pm_init
functions for each platform.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
On OMAP4 panda board, there have been several bug reports about boot
hang and lock-ups with CPU_IDLE enabled. The root cause of the issue
is missing interrupts while in idle state. Commit cb7094e8 {cpuidle / omap4 :
use CPUIDLE_FLAG_TIMER_STOP flag} moved the broadcast notifiers to common
code for right reasons but on OMAP4 which suffers from a nasty ROM code
bug with GIC, commit ff999b8a {ARM: OMAP4460: Workaround for ROM bug ..},
we loose interrupts which leads to issues like lock-up, hangs etc.
Patch reverts commit cb7094 {cpuidle / omap4 : use CPUIDLE_FLAG_TIMER_STOP
flag} and 54769d6 {cpuidle: OMAP4: remove timer broadcast initialization} to
avoid the issue. With this change, OMAP4 panda boards, the mentioned
issues are getting fixed. We no longer loose interrupts which was the cause
of the regression.
Fixes: cb7094e8 (cpuidle / omap4 : use CPUIDLE_FLAG_TIMER_STOP flag)
Fixes: ff999b8a (cpuidle: OMAP4: remove timer broadcast initialization)
Cc: stable@vger.kernel.org # v3.9+
Cc: Roger Quadros <rogerq@ti.com>
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Reported-tested-by: Roger Quadros <rogerq@ti.com>
Reported-tested-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
code into drivers.
Basic build, boot, and PM test results are available here:
http://www.pwsan.com/omap/testlogs/prcm-cleanup-v3.16/20140515213244/
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Merge tag 'for-v3.16/prcm-cleanup-a' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.16/prcm
Some OMAP PRCM cleanup patches. These help prepare to convert the PRCM
code into drivers.
Basic build, boot, and PM test results are available here:
http://www.pwsan.com/omap/testlogs/prcm-cleanup-v3.16/20140515213244/
Conflicts:
arch/arm/mach-omap2/cm3xxx.c
arch/arm/mach-omap2/cm44xx.c
Also fixed up new section mismatch warnings.
Commit c66d039197 broke NAND for non-DT boot on all OMAP2 and OMAP3
boards using board_nand_init(). Following error is seen at boot
[ 0.154998] (null): Unsupported NAND ECC scheme selected
For OMAP2 and OMAP3 platforms, the ecc_opt parameter in platform data
must be set to OMAP_ECC_HAM1_CODE_HW to work properly.
Tested on omap3-beagle c4.
Fixes: c66d039197 (mtd: nand: omap: combine different flavours of 1-bit hamming ecc schemes)
Cc: stable@vger.kernel.org # v3.12+
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
"choppy" audio playback on OMAP5. The other applies an OMAP3630 fix
for clock rate setting for camera to other OMAP3 chips.
Basic build, boot, and PM test results are available here:
http://www.pwsan.com/omap/testlogs/prcm-fixes-b-v3.15-rc/20140514112639/
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Merge tag 'for-v3.15-rc/omap-fixes-b' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.15/fixes-v3
Two small OMAP fixes for v3.15-rc. One fixes "slow motion" or
"choppy" audio playback on OMAP5. The other applies an OMAP3630 fix
for clock rate setting for camera to other OMAP3 chips.
Basic build, boot, and PM test results are available here:
http://www.pwsan.com/omap/testlogs/prcm-fixes-b-v3.15-rc/20140514112639/
The Kconfig symbol PANEL_SHARP_LQ043T1DG01 was removed in v2.6.38. The
check for CONFIG_PANEL_SHARP_LQ043T1DG01 and its MODULE variant has
evaluated to false ever since. Remove that check.
Signed-off-by: Paul Bolle <pebolle@tiscali.nl>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Checks for CONFIG_OMAP2_VENC_OUT_TYPE_SVIDEO and
CONFIG_OMAP2_VENC_OUT_TYPE_COMPOSITE were added in v2.6.35. But the
related Kconfig symbols have never been added to the tree. Remove these
checks.
Initialize connector_type to OMAP_DSS_VENC_TYPE_COMPOSITE explicitly.
That's what's happening currently: OMAP_DSS_VENC_TYPE_COMPOSITE equals
zero and connector_type remains zero since both checks currently fail.
Signed-off-by: Paul Bolle <pebolle@tiscali.nl>
Signed-off-by: Tony Lindgren <tony@atomide.com>
SoC specific late_init call is now registered during PRM init, and will
be called automatically by PRM core. This helps to get rid of some
redundant initcalls and cpu_is_X checks from the PRM code.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
prm_features flag will contain SoC specific feature enabler flags. Initially
IO wakeup is added under this. Helps to get rid of runtime cpu_is_X checks.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
This helps to make the PRM registration modular, and also gets rid of a
cpu type check done later.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Done in preparation to make PRM its own driver, as the cpu_is_XXX calls are
not available outside mach-omap2 folder.
The init functions are called only from cpu specific init chain, and thus
don't need to double check against cpu type.
The exit calls check against the data provided during init-time registration
and thus don't need cpu check either.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
[paul@pwsan.com: updated to apply]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Some of the includes are totally unnecessary, remove some others in
preparation to make the PRCM its own driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
[paul@pwsan.com: updated to apply; fixed build error on OMAP2xxx-only configs]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
OMAP44XX_CM*_REGADDR macros should be avoided, instead use the cm_base*
iomaps.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Done in preparation to move the CM driver to its own driver folder.
These drivers will not have access to functionality under mach-omap2 anymore.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Done in preparation to move cm/prm to drivers. These will still use
omap_test_timeout, but will not have access to common.h header under
mach-omap2 anymore.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
For SOCs with dt enabled, device should be build through device tree.
Prevent device build call from platform code, if device tree is
enabled.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add nodes for the Super Speed USB controllers, omap-control-usb,
USB2 PHY and USB3 PHY devices.
Remove ocp2scp1 address space from hwmod data as it is
now provided via device tree.
CC: Benoît Cousson <bcousson@baylibre.com>
Reviewed-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add hwmod data for dss core, dispc dsi1, dsi2, rfbi and hdmi. It's more
or less similar to omap4 hwmod data.
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
All audio related omap_hwmod_ocp_if *_dma can be removed from the data since
we can just add the user flag to the non dma structure.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
McPDM need to be configured to NO_IDLE mode when it is in used otherwise
vital clocks will be gated which results 'slow motion' audio playback.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Cc: <stable@kernel.org>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Add support for OMAP3 ROM Random Number Generator via
pdata-quirks.
Signed-off-by: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Remove a few OMAP34XX_CM_REGADDR defines and replace these with offset
based register accesses instead.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Add DSS features for AM43xx.
Signed-off-by: Sathya Prakash M R <sathyap@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.
Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
We are currently disabling the init of voltage scaling
for device tree. With the voltage scaling problems fixed
for omap3 in general, there's no need to disable the voltage
scaling init for device tree based booting.
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Nishanth Menon <nm@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Currently we're attempting to use a static value for the
voltctrl register that only works for controlling the PMIC
over I2C4. For using sys_off_mode signaling, we need to update
update clksetup, voltsetup1, voltsetup2 and voltctrl registers
dynamically depending on the idle state.
So let's fix this by configuring things for I2C4 controlled idle
and sys_off_mode pin controlled idle, and then write the
configured register values depending on the idle state. This
is similar what N900 kernel is doing too.
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Nishanth Menon <nm@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Commit c589eb3869 (ARM: OMAP3: VC: calculate ramp times)
started using regulator slew rates for calculating the idle
mode start-up times. This works fine for I2C4 controlled
regulator scaling as the regulators are never completely
turned off.
For sys_off_mode pin controlled PMIC scripts, the slew rate
based calculations won't work at all as the regulators are
completely turned off and the start-up time is much longer.
This means currently omap3_set_off_timings currently has
zero chance of working on any real hardare. The current code
is broken in at least the following ways:
1. It attempts to use the default ULONG_MAX value for the
oscillator start-up value as we're currently never
initializing the start-up value.
2. It relies on a magic number potentially set by the
bootloader for volsetup2 register.
3. If no magic value is passed, it attempts to calculate
voltsetup2 register based on the regulator slew rate.
This won't work as there is roughly at least five
times the delay needed for turning on vdd1 and vdd2
regulators.
4. It does duplicate register write to OMAP3_PRM_VOLTOFFSET
5. It duplicates the code for omap_usec_to_32k unnecessarily
6. It initialized global registers twice, once for each channel
Let's just remove the broken code and call omap3_set_i2c_timings
directly, we're better off with this function doing nothing until
it's fixed. And otherwise further fixes to omap3_set_off_timings
will be unreadable.
And let's get rid of omap3_set_clksetup as that's not needed
for off-idle controlled by I2C4 as in that case the oscillator
is never shut down.
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Nishanth Menon <nm@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
While debugging legacy mode vs device tree booted PM regressions,
I noticed that omap3 is not toggling sys_clkreq and sys_off_mode
pins like it should.
The sys_clkreq and sys_off_mode pins are not toggling because of
the following issues:
1. The default polarity for the sys_off_mode pin is wrong.
OFFMODE_POL needs to be cleared for sys_off_mode to go down when
hitting off-idle, while CLKREQ_POL needs to be set so sys_clkreq
goes down when hitting retention.
2. The values for voltctrl register need to be updated dynamically.
We need to set either the retention idle bits, or off idle bits
in the voltctrl register depending the idle mode we're targeting
to hit.
Let's fix these two issues as otherwise the system will just
hang if any twl4030 PMIC idle scripts are loaded. The only case
where the system does not hang is if only retention idle over I2C4
is configured by the bootloader.
Note that even without the twl4030 PMIC scripts, these fixes will
do the proper signaling of sys_clkreq and sys_off_mode pins, so
the fixes are needed to fix monitoring of PM states with LEDs or
an oscilloscope.
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Nishanth Menon <nm@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The only difference from the dra74x devices is the missing .smp entry.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Use of const init definition must use __initconst so replace
all such instances where __initdata is used.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The variable use_gptimer_clksrc is only used by two __init functions,
So we can freely free it after boot.
Signed-off-by: Oussama Ghorbel <ghorbel@pivasoftware.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Here's a redo of the patch [1] that effectively does the same
thing but is the right way to do things by using ENDPROC instead.
The firmware correctly switches to THUMB before entry.
The patch applies ontop of the earlier patch [1].
[1] https://lkml.org/lkml/2014/4/22/1044
Suggested-by: Dave Martin <Dave.Martin@arm.com>
Cc: Dave Martin <Dave.Martin@arm.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Nishanth Menon <nm@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Joel Fernandes <joelf@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Commit 7b2e127759 ("ARM: OMAP3: clock:
Back-propagate rate change from cam_mclk to dpll4_m5") enabled clock
rate back-propagation from cam_mclk do dpll4_m5 on OMAP3630 only.
Perform back-propagation on other OMAP3 platforms as well.
Reported-by: Jean-Philippe François <jp.francois@cynove.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: <stable@kernel.org>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
On my DRA7 system, when the kernel is built in Thumb-2 mode, the secondary CPU
(Cortex A15) fails to come up causing SMP boot on second CPU to timeout. This
seems to be because the CPU is in ARM mode once the ROM hands over control to
the kernel. Switch to Thumb-2 mode if required once the kernel is control of
secondary CPU. On OMAP4 on the other hand, it appears to be in Thumb-2 mode on
entry so this is not required and SMP boot works as is.
Also corrected a spurious '+' and updated copyright information.
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Nishanth Menon <nm@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Joel Fernandes <joelf@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
At least the smc91x driver expects the device to be at 0x300
offset from bus base address. This does not work currently
for GPMC when booted in device tree mode as it attempts to
remap the the allocated GPMC partition to the address
configured by the device tree plus the device offset.
Note that this works just fine when booted with legacy mode.
Let's fix the issue by just ignoring any device specific
offset while remapping. And let's make sure the remap
address confirms to the GPMC 16MB minimum granularity
as listed in the TRM for GPMC_CONFIG7 BASEADDRESS bits.
Otherwise we can get something like this:
omap-gpmc 6e000000.gpmc: cannot remap GPMC CS 1 to 0x01000300
Cc: Pekon Gupta <pekon@ti.com>
Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
I noticed a regression where the omap sys_clkreq signal will never
trigger for omap3 when booted with device tree while it triggers
when booted in legacy mode. This means voltage scaling does not
do anything when booted with device tree.
Turns out the reason is we fail to initialize the SmartReflex
enable bit in twl4030 with the following error:
twl: not initialized
And that happens because we are wrongly tinkering with the twl4030
registers in arch/arm/mach-omap2/omap_twl.c before the driver is
initialized. Looking at the the SmartReflex bit enable code in
omap_twl.c, we need to always set it.
So let's fix the issue by always enabling the twl4030 SmartReflex
bit in the drivers/mfd/twl-core.c probe, and drop the related
code in omap_twl.c.
Note that we still have some twl4030 tinkering left in omap_twl.c
for the twl6030 case, but that's a different patch.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
If gpmc_cs_remap() fails we will get an error because we are calling
release_resource() on an uninitialized resource. Let's fix that by
checking the resource flags. And while at it, let's also make
gpmc_cs_delete_mem() use the res pointer that we already have to
avoid confusion.
Without this patch we can get the following error:
omap-gpmc 6e000000.gpmc: cannot remap GPMC CS 1 to 0x01000300
Unable to handle kernel NULL pointer dereference at virtual address 00000018
...
(gpmc_cs_free+0x94/0xc8)
(gpmc_probe_generic_child+0x178/0x1ec)
(gpmc_probe_dt+0x1bc/0x2cc)
(gpmc_probe+0x250/0x44c)
(platform_drv_probe+0x3c/0x6c)
(really_probe+0x74/0x208)
(driver_probe_device+0x34/0x50)
(bus_for_each_drv+0x60/0x8c)
(device_attach+0x80/0xa4)
(bus_probe_device+0x88/0xb0)
(device_add+0x320/0x450)
(of_platform_device_create_pdata+0x80/0x9c)
(of_platform_bus_create+0xd0/0x170)
(of_platform_bus_create+0x12c/0x170)
(of_platform_populate+0x60/0x98)
(pdata_quirks_init+0x30/0x48)
(customize_machine+0x20/0x48)
(do_one_initcall+0x2c/0x14c)
(do_basic_setup+0x98/0xd8)
(kernel_init_freeable+0x12c/0x1e0)
(kernel_init+0x8/0xf0)
(ret_from_fork+0x14/0x2c)
Code: e1a04000 e59f0070 eb195136 e5942010 (e5923018)
Cc: Pekon Gupta <pekon@ti.com>
Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org>
Signed-off-by: tony Lindgren <tony@atomide.com>
no functional changes, just renaming the function
in order to make it slightly clearer what it should
be used for, also matching the driver name.
Signed-off-by: Felipe Balbi <balbi@ti.com>
A few OMAP hwmod and clock fixes for v3.15-rc. Probably the most useful
fix is the AM43xx DPLL patch.
Basic build, boot, and PM test results are here:
http://www.pwsan.com/omap/testlogs/prcm-fixes-a-v3.15-rc/20140411130021/
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Merge tag 'for-v3.15-rc/omap-fixes-a' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.15/fixes
OMAP hwmod and clock fixes for v3.15-rc
A few OMAP hwmod and clock fixes for v3.15-rc. Probably the most useful
fix is the AM43xx DPLL patch.
Basic build, boot, and PM test results are here:
http://www.pwsan.com/omap/testlogs/prcm-fixes-a-v3.15-rc/20140411130021/
Do not try to initialize display for DT boot, since omapdss
is now initialized via Device Tree. Without this patch the
display subsystem does not properly come up.
Signed-off-by: Sebastian Reichel <sre@kernel.org>
Acked-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Bug was introduced by commit 'f92d959: ARM: OMAP2+: hwmod:
Extract no-idle and no-reset info from DT'
There were 2 versions of the patch posted which resulted in the above
commit. While v1 [1] had the bug, v2 [2] had it fixed.
However v1 apparently seemed to have been pulled in by mistake
introducing the bug.
Given of_find_property() does return NULL when the node passed is
NULL, it did not introduce any functional issues as such, just the
fact that the second if check was executed unnecessarily.
[1] https://www.mail-archive.com/linux-omap@vger.kernel.org/msg94220.html
[2] http://www.spinics.net/lists/linux-omap/msg98490.html
Cc: Nishanth Menon <nm@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Fixes: f92d9597f7 ("ARM: OMAP2+: hwmod: Extract no-idle and no-reset info from DT")
Signed-off-by: Paul Walmsley <paul@pwsan.com>
On AM43xx, if a PLL is in bypass at kernel init, the code in
omap2_get_dpll_rate() will not realize this and will try to calculate
the clock rate using the multiplier and the divider, resulting in
errors.
omap2_init_dpll_parent() has similar issue.
Add the missing soc_is_am43xx() check to make the code work on AM43xx.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Sathya Prakash M R <sathyap@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
