This allows the input clocks to the Exynos AudioSS block to be
specified via device-tree bindings. Default names will be used
when an input clock is not given.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* Several patches fixing up incorrectly defined register addresses and
bitfield offsets that could lead to undefined operation when accessing
respective registers or bitfields.
1) clk: exynos5250: fix sysmmu_mfc{l,r} gate clocks
2a) clk: samsung: exynos5250: Fix ACP gate register offset
2b) clk: samsung: exynos5250: Add MDMA0 clocks
2c) ARM: dts: exynos5250: Fix MDMA0 clock number
3) clk: samsung: exynos4: Correct SRC_MFC register
All three issues have been present since Exynos5250 and Exynos4 clock
drivers were added by commits 6e3ad26816 ("clk: exynos5250:
register clocks using common clock framework") and e062b57177
("clk: exynos4: register clocks using common clock framework")
respectively.
* Patch to fix automatic disabling of Exynos5250 sysreg clock that could
cause undefined operation of several peripherals, such as USB, I2C,
MIPI or display block.
4) clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg
clock
Present since Exynos5250 clock drivers was added by commits
6e3ad26816 ("clk: exynos5250: register clocks using common clock
framework").
* Patch fixing compilation warning in clk-exynos-audss driver when
CONFIG_PM_SLEEP is disabled.
5) clk: exynos: File scope reg_save array should depend on PM_SLEEP
Present since the driver was added by commit 1241ef94cc ("clk:
samsung: register audio subsystem clocks using common clock
framework").
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.22 (GNU/Linux)
iQIcBAABAgAGBQJSxY6TAAoJEIv3Hb8G/XruUcgP/001H5qqDZWtEk2Z1XvOUPgF
MfFprrNcPpLhLmBnvDpR5mUrcMIp4t/4GcWClmX58zcsZfcQP5YF81oGGiQy+U13
Yu94H+sWihrms5h8GSkqEhB5YSvcIOfs4rtAeNl/g2su7i+l4loF/xofXpj09+qp
xnmKJ8yfB5RD822StgrkoMu7vxzYyK05j8IasSH54vsO9X3Z3jTWuAKdQFKZoZp4
xBGjtIwoyyHndWAlhl1nIj1dvaDgx+gF25qRUrfShfE51R4BNzmvpgiN1mpQTjCl
JpYDJqZ1h7FL883ZXiz7SfRVv4H2GaEWqz+zxgVfHkO45lIL3Eyn1zhSKas4pRFH
KZscKBvT/YEgIQjBW4+VdMuMM0NWIzvYp1BM2/l88KvUgXYiS0EOM5UjYJatKwIO
MW4ZLpIsMiJlN8OygBTaZOZQaY8rbbdVn5KFsgkL0zl7uZzmbYCqhxKrXZfTKyx/
ieEGRmqjrcuguVDPNSsd9TZ/LUm3kTCSzpr3gvAXjK+29DbVrs6fX1lQ0RCxvACQ
8gBjD6ZsVFcsGSbWbPEoDi+qtKielZBjbSrgTDNkRqE/6yqg+UUZVSJJ6kkEA14o
swE+8mGrUhdv5TvpTjJactnBZeUpFbmLm4TE/r695dfwcr6wX7cK41gMVo7bE9fk
2rYzz35ed29q8OfJI/54
=0B0x
-----END PGP SIGNATURE-----
Merge tag 'samsung-clk-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk into clk-fixes
Samsung Clock fixes for 3.13-rc7
* Several patches fixing up incorrectly defined register addresses and
bitfield offsets that could lead to undefined operation when accessing
respective registers or bitfields.
1) clk: exynos5250: fix sysmmu_mfc{l,r} gate clocks
2a) clk: samsung: exynos5250: Fix ACP gate register offset
2b) clk: samsung: exynos5250: Add MDMA0 clocks
2c) ARM: dts: exynos5250: Fix MDMA0 clock number
3) clk: samsung: exynos4: Correct SRC_MFC register
All three issues have been present since Exynos5250 and Exynos4 clock
drivers were added by commits 6e3ad26816 ("clk: exynos5250:
register clocks using common clock framework") and e062b57177
("clk: exynos4: register clocks using common clock framework")
respectively.
* Patch to fix automatic disabling of Exynos5250 sysreg clock that could
cause undefined operation of several peripherals, such as USB, I2C,
MIPI or display block.
4) clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg
clock
Present since Exynos5250 clock drivers was added by commits
6e3ad26816 ("clk: exynos5250: register clocks using common clock
framework").
* Patch fixing compilation warning in clk-exynos-audss driver when
CONFIG_PM_SLEEP is disabled.
5) clk: exynos: File scope reg_save array should depend on PM_SLEEP
Present since the driver was added by commit 1241ef94cc ("clk:
samsung: register audio subsystem clocks using common clock
framework").
- Add the initial i.MX50 SoC support
- Support device tree boot for i.MX35
- Move imx5 clock driver to use macros for clock ID
- Some random updates and non-critical fixes on clock drivers
- A few defconfig updates and minor cleanups
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQEcBAABAgAGBQJSwiPBAAoJEFBXWFqHsHzO3/AIALlP6m/7taIQW5wO4o4aqdwk
GsN7IdsfWH/biG9VyxgpIoJKUqaOJckGA0eyLSeEG7p78xlf0n7cVPUNwzz9z1Vc
zxLSaVNznVOa4fTIsbMK9U+gUP931hjXskxD3tH98MUFqlM0JLQYoofr/lXG7Esf
N2p8B9aUND3WSxDa+d+CsW0B3FBj1piOQDMDgrdc3p7kjcAJs31KaKfUa06o7gzM
a81OaD9Vk0ONf44wh1LGlg0hDRsatQOa4tUTimeV14CnESKqsKxT4qAJ6pZLdfOt
KyRqSk4f4mkpimv4bGdhXTIsIko1CD9wg7G9fsSaolh3OEP0yyNf1savR1fmwCI=
=Hhbl
-----END PGP SIGNATURE-----
Merge tag 'imx-soc-3.14' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/soc
From Shawn Guo:
i.MX SoC changes for 3.14:
- Add the initial i.MX50 SoC support
- Support device tree boot for i.MX35
- Move imx5 clock driver to use macros for clock ID
- Some random updates and non-critical fixes on clock drivers
- A few defconfig updates and minor cleanups
* tag 'imx-soc-3.14' of git://git.linaro.org/people/shawnguo/linux-2.6: (37 commits)
ARM: imx: improve the comment of CCM lpm SW workaround
ARM: imx: improve status check of clock gate
ARM: imx: add necessary interface for pfd
ARM: imx_v6_v7_defconfig: Select CONFIG_REGULATOR_PFUZE100
ARM: imx_v6_v7_defconfig: Select MX35 and MX50 device tree support
ARM: imx: Add cpu frequency scaling support
ARM i.MX35: Add devicetree support.
ARM: imx: update imx_v6_v7_defconfig
ARM: imx6sl: Add missing spba clock to clock tree
ARM: imx6sl: Add missing pll4_audio_div to the clock tree
ARM: imx6: Derive spdif clock from pll3_pfd3_454m
ARM: imx: use __initconst for const init definition
ARM i.MX5: fix obvious typo in ldb_di0_gate clk definition
ARM i.MX5: set CAN peripheral clock to 24 MHz parent
ARM: imx: pllv1: Fix PLL calculation for i.MX27
ARM i.MX5: fix "shift" value for lp_apm_sel on i.MX50 and i.MX53
ARM: imx: imx53: Add SATA PHY clock
ARM: imx_v6_v7_defconfig: Enable STMPE touchscreen
ARM: imx: rename IMX6SL_CLK_CLK_END to IMX6SL_CLK_END
ARM: imx: select PINCTRL at sub-architecure level
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Document the device tree binding for Broadcom Kona architecture
clock control units and clocks. Kona device nodes are represented
with compatible strings having "bcm11351" in their name.
Kona clocks are managed by "clock control units" (CCUs). Each CCU
has a device tree node, and within that node are defined the names
of the clocks provided by the CCU.
The BCM281xx family of SoCs use Kona CCUs and clocks.
Signed-off-by: Alex Elder <elder@linaro.org>
Reviewed-by: Matt Porter <matt.porter@linaro.org>
Reviewed-by: Tim Kryger <tim.kryger@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Christian Daudt <bcm@fixthebug.org>
Use clock defines in order to make devicetrees more
human readable.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Adds gate clock for MDMA0 on Exynos5250 SoC. This is needed to ensure
that the clock is enabled when MDMA0 is used on systems on which
firmware gates the clockby default.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
[t.figa: Updated patch description.]
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
This patch adds support for the external clock outputs on the
Allwinner A20 SoC. The clock outputs are similar to "module 0"
type clocks, with different offsets and widths for clock factors.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Emilio López <emilio@elopez.com.ar>
This commit implements support for the "module 0" type of clocks, as
used by MMC, IR, NAND, SATA and other components.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Mike Turquette <mturquette@linaro.org>
This commit implements PLL5 and PLL6 support on the sunxi clock driver.
These PLLs use a similar factor clock, but differ on their outputs.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Mike Turquette <mturquette@linaro.org>
This commit adds gating support to PLL1 on the clock driver. This makes
the PLL1 implementation fully compatible with PLL4 as well.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Bringing in the tegra dma/reset framework cleanup as a base for the DT changes.
* tegra/dma-reset-rework: (320 commits)
spi: tegra: checking for ERR_PTR instead of NULL
ASoC: tegra: update module reset list for Tegra124
clk: tegra: remove bogus PCIE_XCLK
clk: tegra: remove legacy reset APIs
ARM: tegra: remove legacy DMA entries from DT
ARM: tegra: remove legacy clock entries from DT
USB: EHCI: tegra: use reset framework
Input: tegra-kbc - use reset framework
serial: tegra: convert to standard DMA DT bindings
serial: tegra: use reset framework
spi: tegra: convert to standard DMA DT bindings
spi: tegra: use reset framework
staging: nvec: use reset framework
i2c: tegra: use reset framework
ASoC: tegra: convert to standard DMA DT bindings
ASoC: tegra: allocate AHUB FIFO during probe() not startup()
ASoC: tegra: call pm_runtime APIs around register accesses
ASoC: tegra: use reset framework
dma: tegra: register as an OF DMA controller
dma: tegra: use reset framework
...
Signed-off-by: Olof Johansson <olof@lixom.net>
This series converts the Tegra DTs and drivers to use the common/
standard DMA and reset bindings, rather than custom bindings. It also
adds complete documentation for the Tegra clock bindings without
actually changing any binding definitions.
This conversion relies on a few sets of patches in branches from outside
the Tegra tree:
1) A patch to add an DMA channel request API which allows deferred probe
to be implemented.
2) A patch to implement a common part of the of_xlate function for DMA
controllers.
3) Some ASoC patches (which in turn rely on (1) above), which support
deferred probe during DMA channel allocation.
4) The Tegra clock driver changes for 3.14.
Consequently, this branch is based on a merge of all of those external
branches.
In turn, this branch is or will be pulled into a few places that either
rely on features introduced here, or would otherwise conflict with the
patches:
a) Tegra's own for-3.14/powergate and for-4.14/dt branches, to avoid
conflicts.
b) The DRM tree, which introduces new code that relies on the reset
controller framework introduced in this branch, and to avoid
conflicts.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJSr3AnAAoJEMzrak5tbycxfMwQAMeffTFreJqDiQ4Vj0XmuhSn
RFlXiZQsWtQ6gGgNfKyDsXzDMaz1KDAabcUYRcZwrluxuSCPBcK1JirCj5R8uRY7
LDZFX92CO8zRgiij0mhgokV4zzuEQ56q1uhPxqI3o+wG3v44jlMSMgFHQJUevdET
aKr2Pss8Hb00XDztnpxprs6FUoU/W99NRH0i/5znbBwuHqYFP37zlKe2MRwbqDwR
AMgkrnGoawe85Stz4p/iR9pCLpAMa0dH94V4JrAP4+IQrl0DEKWbrolpQHii4gzh
NCGazMELTqkaZaorC/n1SmczH1kTj4vcjbbmeB8dwS8Vqhr+uf7W1oLlJ46TUOsp
ESO0uD2GfpHKQQwLxEfgjfmwsIUMbdWHef8f2HUuvl6Js+LCpaPkxd52Pt/qL4sU
0sKqTbldRZXzGhvwa0/MK32WhmH4v31s7IZAg5A2YxqDR6yWryl7legWyvrI96C0
OlmVe1C/2NGk0QCfK0G/xTa9V7YzMfj8k4ICSZOgUoF4BeGGj6d3svWvLbKbbrU1
0fVvR7aCm78pRXixI6kURpj9D0mEfqus9Hx7VoWcL0TS4QH2dSYlGI+jDCiliQmj
+kWrZWHsASSvPmUZk4RBNaviCbnGU8/t5nNdJSdFIUM/PIswzZ4GaAu6gdVksIY8
hcx410PyAzTZL2lENamE
=8T7+
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-3.14-dmas-resets-rework' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/cleanup
From Stephen Warren:
ARM: tegra: implement common DMA and resets DT bindings
This series converts the Tegra DTs and drivers to use the common/
standard DMA and reset bindings, rather than custom bindings. It also
adds complete documentation for the Tegra clock bindings without
actually changing any binding definitions.
This conversion relies on a few sets of patches in branches from outside
the Tegra tree:
1) A patch to add an DMA channel request API which allows deferred probe
to be implemented.
2) A patch to implement a common part of the of_xlate function for DMA
controllers.
3) Some ASoC patches (which in turn rely on (1) above), which support
deferred probe during DMA channel allocation.
4) The Tegra clock driver changes for 3.14.
Consequently, this branch is based on a merge of all of those external
branches.
In turn, this branch is or will be pulled into a few places that either
rely on features introduced here, or would otherwise conflict with the
patches:
a) Tegra's own for-3.14/powergate and for-4.14/dt branches, to avoid
conflicts.
b) The DRM tree, which introduces new code that relies on the reset
controller framework introduced in this branch, and to avoid
conflicts.
* tag 'tegra-for-3.14-dmas-resets-rework' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (30 commits)
spi: tegra: checking for ERR_PTR instead of NULL
ASoC: tegra: update module reset list for Tegra124
clk: tegra: remove bogus PCIE_XCLK
clk: tegra: remove legacy reset APIs
ARM: tegra: remove legacy DMA entries from DT
ARM: tegra: remove legacy clock entries from DT
USB: EHCI: tegra: use reset framework
Input: tegra-kbc - use reset framework
serial: tegra: convert to standard DMA DT bindings
serial: tegra: use reset framework
spi: tegra: convert to standard DMA DT bindings
spi: tegra: use reset framework
staging: nvec: use reset framework
i2c: tegra: use reset framework
ASoC: tegra: convert to standard DMA DT bindings
ASoC: tegra: allocate AHUB FIFO during probe() not startup()
ASoC: tegra: call pm_runtime APIs around register accesses
ASoC: tegra: use reset framework
dma: tegra: register as an OF DMA controller
dma: tegra: use reset framework
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Merging in external dependencies for the Tegra DMA and reset controller
refactoring from external trees.
Per Stephen Warren, the stability of these branches have been negotiated
with the relevant parties (Vinod/Mark/Mike)
* depends/asoc-dma:
ASoC: dmaengine: fix deferred probe detection
ASoC: dmaengine: support deferred probe for DMA channels
dma: add channel request API that supports deferred probe
ASoC: dmaengine: add custom DMA config to snd_dmaengine_pcm_config
ASoC: don't leak on error in snd_dmaengine_pcm_register
ASoC: restructure dmaengine_pcm_request_chan_of()
ASoC: generic-dmaengine-pcm: Set BATCH flag when residue reporting is not supported
ASoC: Add resource managed snd_dmaengine_pcm_register()
* depends/dma-of:
dma: add dma_get_any_slave_channel(), for use in of_xlate()
* depends/tegra-clk: (42 commits)
clk: tegra: fix __clk_lookup() return value checks
clk: tegra: Do not print errors for clk_round_rate()
clk: tegra: Initialize DSI low-power clocks
clk: tegra: add FUSE clock device
clk: tegra: Properly setup PWM clock on Tegra30
clk: tegra: Initialize secondary gr3d clock on Tegra30
clk: tegra114: Initialize clocks needed for HDMI
clk: tegra124: add suspend/resume function for tegra_cpu_car_ops
clk: tegra124: add wait_for_reset and disable_clock for tegra_cpu_car_ops
clk: tegra124: Add support for Tegra124 clocks
clk: tegra124: Add new peripheral clocks
clk: tegra124: Add common clk IDs to clk-id.h
clk: tegra: add TEGRA_PERIPH_NO_GATE
clk: tegra: add locking to periph clks
clk: tegra: Add periph regs bank X
clk: tegra: Add support for PLLSS
clk: tegra: move tegra20 to common infra
clk: tegra: move tegra30 to common infra
clk: tegra: introduce common gen4 super clock
clk: tegra: move PMC, fixed clocks to common files
...
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch adds support for accuracy retrieval on fixed clocks.
It also adds a new dt property called 'clock-accuracy' to define the clock
accuracy.
This can be usefull for oscillator (RC, crystal, ...) definitions which are
always given an accuracy characteristic.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Add support for using emev2 SMU clocks with DT
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.14 (GNU/Linux)
iQIcBAABAgAGBQJSt40hAAoJENfPZGlqN0++JzgP/1E4U6AovB3HxLUvyp6nT4oW
xwkPRfAMxiZRWuEi8QnZSBa6XxrAyublAisuZ+5QXFbQDwAbLpPuX/eNZ5sThCqp
L4/msoptAUVWk2fiHx/wiTxJBhBH+loDkShAq6SooqGrSg1oP7uhq2WJrhK60XHx
GTUgLFDSr7Cjm9yznOYKn74iYiWh5ywv0rIqnpbdjd098Fwv0lC0YcLKq4eXS8+u
CBzYgkaezZ1YDs/rsvGiyJPvHhmUnDQ+mo9fMoYSKZ+IR0RWc84vH+5aWuZ8qYZB
AtuQSpJxBD6BFRuR+JDNSH1fAnzTyEDZasyEB8mxr3n8qnE1MKkhcxiLbuHUWVeu
pVj7dShut+8ovPOMGiaJ4k32D6aQlnSMx99fmxBscBNXcs9dyCJxztpPLMc09Et9
HhMKwmfhzHTyEbfLRAr7zVARcyjjWAd1OnoDVINWB1FBxJH9rMSNeBIjqIphm/Cm
H/z1n+Z+DVexClvpayona2eL/TEFmPefPKCXl5cjCmUOwJsyZ7UPmCxMA6srBh6F
wYH2zQT5GfbqDx8643RWXxIovTkUPsiiWR4tIydjB9fCV+pg/ZGkKxnzq4nsAkl1
zY7S5SeYYYSMhRngIBsHpXY9JWItdLVw3vC9yybk+OXm/Q+cXIn/DBcIQsDzdAcQ
EcmF19/7VTKoeluK99zH
=NhhY
-----END PGP SIGNATURE-----
Merge tag 'renesas-clock-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into clk-next-shmobile2
Renesas ARM based SoC Clock updates for v3.14
Add support for using emev2 SMU clocks with DT
In some use cases Zynq's FPGA clocks are used as static clock
generators for IP in the FPGA part of the SOC for which no Linux driver
exists and would control those clocks. To avoid automatic
gating of these clocks in such cases a new property - fclk-enable - is
added to the clock controller's DT description to accomodate such use
cases. It's value is a bitmask, where a set bit results in enabling
the corresponding FCLK through the clkc.
FPGA clocks are handled following the rules below:
If an FCLK is not enabled by bootloaders, that FCLK will be disabled in
Linux. Drivers can enable and control it through the CCF as usual.
If an FCLK is enabled by bootloaders AND the corresponding bit in the
'fclk-enable' DT property is set, that FCLK will be enabled by the clkc,
resulting in an off by one reference count for that clock. Ensuring it
will always be running.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add a driver for SILabs 570, 571, 598, 599 programmable oscillators.
The devices generate low-jitter clock signals and are reprogrammable via
an I2C interface.
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Device tree clock binding document for EMMA Mobile EV2 SMU,
And Common clock framework based implementation of it.
Following nodes are defined to describe clock tree.
- renesas,emev2-smu
- renesas,emev2-smu-clkdiv
- renesas,emev2-smu-gclk
These bindings are designed manually based on
19UH0037EJ1000_SMU : System Management Unit User's Manual
So far, reparent is not implemented, and is fixed to index #0.
Clock tree description is not included, and should be provided
by device-tree.
Signed-off-by: Takashi Yoshii <takasi-y@ops.dti.ne.jp>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
MSTP clocks are gate clocks controlled through a register that handles
up to 32 clocks. The register is often sparsely populated.
Those clocks are found on Renesas ARM SoCs.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
DIV6 clocks are divider gate clocks controlled through a single
register. The divider is expressed on 6 bits, hence the name, and can
take values from 1/1 to 1/64.
Those clocks are found on Renesas ARM SoCs.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
The R-Car Gen2 SoCs (R8A7790 and R8A7791) have several clocks that are
too custom to be supported in a generic driver. Those clocks can be
divided in two categories:
- Fixed rate clocks with multiplier and divisor set according to boot
mode configuration
- Custom divider clocks with SoC-specific divider values
This driver supports both.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Update all the Tegra DT bindings to require resets/reset-names properties
where the HW module has reset inputs. Remove any entries from clocks or
clock-names that were only required to identify reset inputs, rather than
referring to real clocks.
This is a DT-ABI-incompatible change. It is the first of two changes
required for me to consider the Tegra DT bindings as stable, the other
being conversion to the common DMA DT bindings.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-By: Terje Bergstrom <tbergstrom@nvidia.com>
DDR3A/B, ARM and PA PLL controllers have clkod register bits for
configuring postdiv values. So use it instead of using fixed
post dividers for these pll controllers. Assume that if fixed-postdiv
attribute is not present, use clkod register value for pistdiv.
Also update the Documentation of bindings to reflect the same.
Cc: Mike Turquette <mturquette@linaro.org
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Enable common clock driver of Hi3620 SoC. clkgate-seperated driver is
used to support the clock gate that enable/disable/status registers
are seperated.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
This patch adds new at91 clks dt bindings documentation.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
The required properties are not named "div" and "mult",
but rather "clock-div" and "clock-mult".
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
bug fixes along with updates to existing clock drivers and the
additional of new clock drivers.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJSgXEHAAoJEDqPOy9afJhJpp4P+gLir1FJsFiD9gK6UmRU2QZ6
zUBAyIyvuIOnXKRAPYD88C2d86ztaH0fMoyd3VBjrqCobS2ybTWCd0u28xsKEFZN
30GkvUYH+mOYaI73u9Q1onHH5qNpfvJAkv+dbXv+BWutzd4ygTjzB1dKSYRL3RtP
2YikqvWzvICJ+P5Med2YKDfE1BkEsA/BDCdynUOdABH4xSG+AI+/2P7TbHGz0bQC
odyT4eh0uA5IlkeOtG8243ysM/u287bJnvBkFzQKkdcv1ZoNWyIytgfpSqldcYCv
bf7OfgQPXqoIUqTlcjxbSyDxH1rBj0hHH2J4Hc+vlVixnu8in4XMjTEN8wJRqH94
W1wbxGM8v7fVj4OgJf//bjXWDZgr692o444ACvv3GHTT1RTD4WwBg9ouJ7faREeQ
06/tJsfgZ7bRaCLKWrdabGxgjUudj8vfGXjnL3DJjztEQEtp9lWuT84phU0kvcH/
JpxDfkxynZSbCHMHiOYAFP2bQjwCisU4vJrNo2jvYARVgGSfbkP9rncXaVjEMQVB
3gsJs9IRRCFTOVJiVVyWjWILPigDl96/pTDEEp33cvAOLHCLsa6RSYXnd+fY7h+W
0iNEuTTmZT3B3bTGMGx7c6beSppgiUFkvpH1KaKwnZI3d4TCutrPOwfzUFe8ULX+
LJzWqln7g/cRfQvmv0US
=wBeW
-----END PGP SIGNATURE-----
Merge tag 'clk-for-linus-3.13' of git://git.linaro.org/people/mturquette/linux
Pull clock framework changes from Mike Turquette:
"The clock changes for 3.13 are an even mix of framework improvements &
bug fixes along with updates to existing clock drivers and the
additional of new clock drivers"
* tag 'clk-for-linus-3.13' of git://git.linaro.org/people/mturquette/linux:
clk: new driver for efm32 SoC
clk: of: helper for determining number of parent clocks
clk/zynq: Fix possible memory leak
clk: keystone: Build Keystone clock drivers
clk: keystone: Add gate control clock driver
clk: keystone: add Keystone PLL clock driver
Documentation: Add documentation for APM X-Gene clock binding
clk: arm64: Add DTS clock entry for APM X-Gene Storm SoC
clk: Add APM X-Gene SoC clock driver
clk: wm831x: get rid of the implementation of remove function
clk: Correct lookup logic in clk_fetch_parent_index()
clk: Use kcalloc() to allocate arrays
clk: Add error handling to clk_fetch_parent_index()
Most of this branch consists of updates, additions and general churn of
the device tree source files in the kernel (arch/arm/boot/dts). Besides
that, there are a few things to point out:
- Lots of platform conversion on OMAP2+, with removal of old board files
for various platforms.
- Final conversion of a bunch of ux500 (ST-Ericsson) platforms as well
- Some updates to pinctrl and other subsystems. Most of these are for
DT-enablement of the various platforms and acks have been collected.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJSgB6cAAoJEIwa5zzehBx3uuEP/0n8b7qgmx2e0HPtx3qlqPiR
3bit2/5MzJNufb46qnYhhE+DF+bo1yfGlrIQK7nBXuv1fMKKlVMoUZ7Ql3EBbPzd
UWrENl2eiapO7D9uN9EZ5WVYu+tKJewU89xkhM70xlCBUHGgQ4k958E8TH9vmELI
Qj1s2UcsYftMF9EH6sbQZ7Jkhrg2M9zVgqUcrqqZT/ZF97174SCEJzAt6n9RGGvr
M9sPOPOIO2D5/tu1oOz1dCQQmATj2r5NYAMOu/jVlvB0OpsCrsFwrTWGHWfssR4z
3uIxcaVb4XgtxCtY9o+C9nJiLGqoENWQS7ScuAx6GTHjn4dwL9OZBMjb/vGGFKQp
dtikMRCaNAkJ8XNl/s8ND+rLzXuPF2KIqkZZz/Nwm02lZq/0OPu0ysBGpdN4C4pk
TRiLxnqE0OZg5cnFQFOMAZF4ABh/0x8cM7a1PPBT5MnTvuH1YrLAuvL5daReU5u1
LlxlFd9rSq8SVn8pBLgKk8RlMkqduDm1HusABnFlzBJMJ0Jy2Ol1X3fPK/8wHq6e
4NedNaQbnx1U5pB2mGIPutkBdVkjK7dKvlDXgYi1sunf5Ake+vej3zJ7u4UfWeIJ
lHJgjnPHdGtZ74RU4/ckp5ba+JHXJ15XAxFKk9XRiOjf+9ciQ4dLRF/JfiSRG2Yc
9NZi38w8M3wC2P7U3dh4
=nH67
-----END PGP SIGNATURE-----
Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC DT updates from Olof Johansson:
"Most of this branch consists of updates, additions and general churn
of the device tree source files in the kernel (arch/arm/boot/dts).
Besides that, there are a few things to point out:
- Lots of platform conversion on OMAP2+, with removal of old board
files for various platforms.
- Final conversion of a bunch of ux500 (ST-Ericsson) platforms as
well
- Some updates to pinctrl and other subsystems. Most of these are
for DT-enablement of the various platforms and acks have been
collected"
* tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (385 commits)
ARM: dts: bcm11351: Use GIC/IRQ defines for sdio interrupts
ARM: dts: bcm: Add missing UARTs for bcm11351 (bcm281xx)
ARM: dts: bcm281xx: Add card detect GPIO
ARM: dts: rename ARCH_BCM to ARCH_BCM_MOBILE (dt)
ARM: bcm281xx: Add device node for the GPIO controller
ARM: mvebu: Add Netgear ReadyNAS 104 board
ARM: tegra: fix Tegra114 IOMMU register address
ARM: kirkwood: add support for OpenBlocks A7 platform
ARM: dts: omap4-panda: add DPI pinmuxing
ARM: dts: AM33xx: Add RNG node
ARM: dts: AM33XX: Add hwspinlock node
ARM: dts: OMAP5: Add hwspinlock node
ARM: dts: OMAP4: Add hwspinlock node
ARM: dts: use 'status' property for PCIe nodes
ARM: dts: sirf: add missed address-cells and size-cells for prima2 I2C
ARM: dts: sirf: add missed cell, cs and dma channel for SPI nodes
ARM: dts: sirf: add missed graphics2d iobg in atlas6 dts
ARM: dts: sirf: add missed chhifbg node in prima2 and atlas6 dts
ARM: dts: sirf: add missed memcontrol-monitor node in prima2 and atlas6 dts
ARM: mvebu: Add the core-divider clock to Armada 370/XP
...
Updates of SoC-near drivers and other driver updates that makes more sense to
take through our tree. In this case it's involved:
- Some Davinci driver updates that has required corresponding platform code
changes (gpio mostly)
- CCI bindings and a few driver updates
- Marvell mvebu patches for PCI MSI support (could have gone through the PCI
tree for this release, but they were acked by Bjorn for 3.12 so we kept them
through arm-soc).
- Marvell dove switch-over to DT-based PCIe configuration
- Misc updates for Samsung platform dmaengine drivers
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJSgBr3AAoJEIwa5zzehBx3QkEP/i0bm4V+AkNV/EXPxqXDf0Re
WIKao/0UjqEfTLSx38F+GlsCdpiPkicPZls0tzAiuqWycx+gMiUlJ7XB+tFmQRk1
RS4KzPQeALFVapjVLtid/Bls9OVI8NcNL1Dx7FISTURzrSzB+kXg7KIsq92SootW
AHUMZbPQNqZoTYcRo9EFEBCm+7QwH1GmWIo5tID6sRhPIsj0xXrw/zOQDK4WDbkv
ZmlR2PNdVTYNuKsWtBcINU5GGNcTCEpnLlHZ9QzVOGyP2M/S93FQdjjm+vDxBRC6
0WsCCFzWc2boSyKrah8xcb7kox7+8HMXUFFAARfOJxvqnMpDCSQnQv0Hb2SiwbkF
7AW90lj+E9KqleSVy1fjGOvx2MV8vhqFMoCYg2TXW2546JADGnCw2JOILfRcqMox
JqIpc84Yhmnv2qFCDxdj9hLYqvhH3RjdLzaLhSfMPc8pjP1StMJzcNi7tN46KVqg
60wU7DvJ0uWfacUGj7VBn88XiZvvJjO/laxj5UcZlS+kQzsysw4Tbriz9UeJK1yl
N0LBl4iA9xn5aUEI/1kL8xzX+h01VodMCe6jIz3JBdE66vCX6d2Tf+zYpNHiGCsH
kBfOpuYc1jVW6qTYqDWgO3IVdDdSGa096AF5vR3MOmtDidblq9QVVxxhDwscqO6J
O0RIcxwZAzQGcO4F50PL
=yCsK
-----END PGP SIGNATURE-----
Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM driver updates from Olof Johansson:
"Updates of SoC-near drivers and other driver updates that makes more
sense to take through our tree. In this case it's involved:
- Some Davinci driver updates that has required corresponding
platform code changes (gpio mostly)
- CCI bindings and a few driver updates
- Marvell mvebu patches for PCI MSI support (could have gone through
the PCI tree for this release, but they were acked by Bjorn for
3.12 so we kept them through arm-soc).
- Marvell dove switch-over to DT-based PCIe configuration
- Misc updates for Samsung platform dmaengine drivers"
* tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (32 commits)
ARM: S3C24XX: add dma pdata for s3c2410, s3c2440 and s3c2442
dmaengine: s3c24xx-dma: add support for the s3c2410 type of controller
ARM: S3C24XX: Fix possible dma selection warning
PCI: mvebu: make local functions static
PCI: mvebu: add I/O access wrappers
PCI: mvebu: Dynamically detect if the PEX link is up to enable hot plug
ARM: mvebu: fix gated clock documentation
ARM: dove: remove legacy pcie and clock init
ARM: dove: switch to DT probed mbus address windows
ARM: SAMSUNG: set s3c24xx_dma_filter for s3c64xx-spi0 device
ARM: S3C24XX: add platform-devices for new dma driver for s3c2412 and s3c2443
dmaengine: add driver for Samsung s3c24xx SoCs
ARM: S3C24XX: number the dma clocks
PCI: mvebu: add support for Marvell Dove SoCs
PCI: mvebu: add support for reset on GPIO
PCI: mvebu: remove subsys_initcall
PCI: mvebu: increment nports only for registered ports
PCI: mvebu: move clock enable before register access
PCI: mvebu: add support for MSI
irqchip: armada-370-xp: implement MSI support
...
This patch adds support for the clocks provided by the Clock Management
Unit of Energy Micro's efm32 Giant Gecko SoCs including device tree
bindings.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
* Low-level debug support for Vybrid
* Support soc bus/device for imx6
* Suspend support for imx6dl and imx6sl
* The imx6q clock updates for PCIe and audio PLL support
* IOMUXC GPR update for fec support
* Some random cleanup
* A few defconfig updates
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQEcBAABAgAGBQJSZI9RAAoJEFBXWFqHsHzOhgkH/RpZ6cvXFFaRdTWQu/SZCXTN
m3Ul0VpuaUp9gsbDNbu//OmqCAsayXaKI7PuJhs885zDKw6R3yMH7hbwXY7z0Qrq
jl9hP1Wzj7oU4CHTQbSDdcO3glUk+jl58a2MrsMsUaXPJTF8iMb8RkatwnReYhiZ
uCBXPwaet7SJTuVQOL1uJmq35LmiROwyAkGsDKnDmphg3ZDUiI9mhqlyOyrS522w
TjmCXrzZQiHkTp12Xo42fIEvE6BF5wCLDlJbq9HRDAlT82CnV62uQC/9os45Hott
H1pJbwdbcdv3+6gUdnWbraukrbhCxT8Yk0As4ljP6YBCxC7Sau+oMh3ii4pvuI0=
=VUrE
-----END PGP SIGNATURE-----
Merge tag 'imx-soc-3.13' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/soc
From Shawn Guo:
The imx/mxs soc changes for 3.13:
* Low-level debug support for Vybrid
* Support soc bus/device for imx6
* Suspend support for imx6dl and imx6sl
* The imx6q clock updates for PCIe and audio PLL support
* IOMUXC GPR update for fec support
* Some random cleanup
* A few defconfig updates
* tag 'imx-soc-3.13' of git://git.linaro.org/people/shawnguo/linux-2.6: (31 commits)
ARM: imx: enable suspend for imx6sl
ARM: imx: ensure dsm_request signal is not asserted when setting LPM
ARM: imx6q: call WB and RBC configuration from imx6q_pm_enter()
ARM: imx6q: move low-power code out of clock driver
ARM: imx: drop extern with function prototypes in common.h
ARM: imx: reset core along with enable/disable operation
ARM: imx: do not return from imx_cpu_die() call
ARM: imx_v6_v7_defconfig: Select CONFIG_PROVE_LOCKING
ARM: imx_v6_v7_defconfig: Enable LEDS_GPIO related options
ARM: mxs_defconfig: Turn off CONFIG_DEBUG_GPIO
ARM: imx: replace imx6q_restart() with mxc_restart()
ARM: mach-imx: mm-imx5: Retrieve iomuxc base address from dt
ARM: mach-imx: mm-imx5: Retrieve tzic base address from dt
ARM: mach-imx: clk-imx51-imx53: Retrieve base address and irq from dt
ARM: mxs_defconfig: Add CHIPIDEA_UDC support
ARM: imx: Include linux/err.h
ARM: imx_v6_v7_defconfig: Add CHIPIDEA_UDC support
ARM: imx_v6_v7_defconfig: Add SPDIF support
ARM: imx6q: clock and Kconfig update for PCIe support
ARM: imx: Add LVDS general-purpose clocks to i.MX6Q
...
Signed-off-by: Olof Johansson <olof@lixom.net>
The Armada 370/XP SoCs have a Core Divider clock providing
several clocks. For now, only the NAND clock is supported.
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The i.MX6 has two general-purpose LVDS clocks that can be driven
from a variety of sources. This patch adds a mux and a gate for
both of these clocks.
Signed-off-by: Sean Cross <xobs@kosagi.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
There's a pll4_audio_div clock, an extra divider for pll4, missing
in current clock tree, thus add it.
Signed-off-by: Nicolin Chen <b42378@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
That documentation was mostly useful when we didn't have any
documentation for those SoCs, which is not the case anymore. Remove
this, since it should live in the DT anyway.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Mark Rutland <mark.rutland@arm.com>
The gated clock documentation referred only to the Orion SoC whereas
it also applied for the Armada 370/XP SoC. This commit updates the
introduction text and also the list of the compatible strings.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Add the driver for the clock gate control which uses PSC (Power Sleep
Controller) IP on Keystone 2 based SOCs. It is responsible for enabling and
disabling of the clocks for different IPs present in the SoC.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
