hdcp 1.x can be used by different interfaces attached to
different frame buffers. Add hdcp 1.x data to the panel
specific data so that hdcp 1.x module can access the
corresponding data.
Change-Id: I19917582aa1a52b11eb04e2031403c09bc0aba9b
CRs-Fixed: 1050304
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Fix the hdcp 1.x sink address where the random number for the
first part of authentication protocol will be written.
Furthermore, fix the read of random number as generated
on the device before it is sent during authentication.
Change-Id: I665008509a2c00d6627e49a5806069747e00eafd
CRs-Fixed: 1050304
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Do not reset interrupt in Display Port driver as HDCP
module also uses same register for interrupts. Use proper
parameters for AUX APIs to avoid communication failures.
CRs-Fixed: 1050304
Change-Id: Ib7b046ca5a0071e571758fd656c86a3fd3be51af
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Program the HDMI/DP core select register during interface setup
since this acts as a mux select for shared interface with LPASS
for audio programming. The mux value is set to 1 for DP and to
0 for HDMI and all other panels.
CRs-Fixed: 1009284
Change-Id: I3283c6255f9cdbbfbffc47057c60b30eb7bdacde
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Update the audio programming sequence for Display Port
to include the selection of the maud/naud values for a
given frequency, programming of the safe to exit level
for the main link, and the calculation of the parity bytes
for each byte of a Secondary Data Packet.
CRs-Fixed: 1009284
Change-Id: I3d83b735a81fed834befca21307cafda89eb5878
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Update the CPR corner switch delay time for the CPRh device
on msmcobalt v2 according to the latest hardware guidelines.
CRs-Fixed: 1064318
Change-Id: I08a385b360d9d0184fd7339194630d8f75a6676f
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Hardware register access logs added for reset sequence is way too
much log but it is necessary for debugging purpose. So create
separate IPC logging buffer for register access and make it as
depends on debug feature so that it can be configured out in
production.
CRs-fixed: 1060274
Change-Id: I690e7af912ce3aee5f0a2817e20f00d6a0ec9608
Signed-off-by: Prashanth Bhatta <bhattap@codeaurora.org>
Update the number of power-freq pair value supported in the debug
interface. Parse the arguments as uint32_t instead of uint64_t which
might cause memory corruption.
CRs-fixed: 1054344
Change-Id: I30492b79b96356177cdcc72e4e2ee656317de500
Signed-off-by: Archana Sathyakumar <asathyak@codeaurora.org>
Ptable and enable node parses the input arguments incorrectly. Parse the
input message into exact number of arguments that are required for the
respective nodes.
CRs-fixed: 1032875
Change-Id: I881f18217b703a497efa4799288dee39a28ea8ab
Signed-off-by: Archana Sathyakumar <asathyak@codeaurora.org>
Add stub regulator devices for msmfalcon because RPM regulator
support is not yet in place.
CRs-Fixed: 1056821
Change-Id: I6845ed3863ab98a06829372ff1a3d460680def30
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
Add a new mixer control to control WSA881x analog gain when
compander is disabled.
Change-Id: I8fd8bf7326f1ea80df1c2fdbb08ebf73aa9e279c
Signed-off-by: Vidyakumar Athota <vathota@codeaurora.org>
Certain frequencies of DP VCO clock are more than 4.29 GHz
and are not supported by clock framework on 32 bit builds,
since it exceeds the maximum value of unsigned long data type.
To fix this issue, change the DP link clock frequencies in order
of KHz in DP FB driver/MMSS cobalt clock driver/DP PLL driver.
Change-Id: I46d9b5c57f94aa1f10df08c4430b617355a82eec
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
Re-enable CONFIG_QCOM_REMOTEQDSS for all supported 32bit
targets i.e. msmcobalt and msmfalcon. It was earlier
disabled due to a build issue which is fixed by 'commit
8ecaa617d5 ("soc: qcom: remoteqdss: Fix build error
on 32bit")'.
Change-Id: I4f8302385010cf2e5c3d9baa717bd2d7d1237853
Signed-off-by: Shiraz Hashim <shashim@codeaurora.org>
The current api which performs the clock reset is moved to use the reset
framework, so support the changes in USB driver for the same. The reset
framework requires to get reset handle and perform assert/deassert of the
resets.
Change-Id: Ifcde1c6af624294cbd1944eaa9b526dd6dcc51de
Signed-off-by: Amit Nischal <anischal@codeaurora.org>
The stack object “ci” has a total size of 8 bytes. Its last 3 bytes
are padding bytes which are not initialized and leaked to userland
via “copy_to_user”.
Git-commit: 681fef8380eb818c0b845fca5d2ab1dcbab114ee
Git-repo: http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git
Signed-off-by: Kangjie Lu <kjlu@gatech.edu>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Dennis Cagle <d-cagle@codeaurora.org>
(cherry picked from commit 681fef8380eb818c0b845fca5d2ab1dcbab114ee)
Change-Id: Idacb2d5ed64654f85fb86fcce0a196223a7ac2af
Read the charger die temperature and its threshold from RR_ADC,
and expose to the userspace through battery PSY.
Read USBIN current and voltage from RR_ADC, and expose to the
userspace through USB PSY.
CRs-Fixed: 1050042
Change-Id: I452a050298a6ab081f64aa2dcf295d2d257bcb32
Signed-off-by: Harry Yang <harryy@codeaurora.org>
Add required settings for command mode 120Hz sharp
panel in msmcobalt for CDP and MTP devices.
CRs-Fixed: 1060888
Change-Id: I58d05466f5e372fb9ce3e0dd49fff07c341f6dc0
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
Per USB 3.1 specification, USB device can draw upto 900mA when
enumerated in super-speed mode and bus is resumed. Fix bug that is
requesting 500mA when bus is resumed when bus is operating in
super-speed mode.
CRs-Fixed: 1063393
Change-Id: I585f4c560f0920d3cb56cce009297b5665abb42e
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
The multimedia PLLs are all in the MX domain on MSMCOBALT. Replace
voting on the CX rail with voting for MX voltages from the clock
driver. In addition, update the MMPLL7 FMAX table.
CRs-Fixed: 1063153
Change-Id: I296d2b151753be599a1db139e36f5e1eabe76791
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Add support to measure the perf and power cluster clocks
via the debug mux on MSMCOBALT.
CRs-Fixed: 1059153
Change-Id: I1682481dfe22deef300ea9bd1db558ae634c9129
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
