Commit graph

536152 commits

Author SHA1 Message Date
Adrien Schildknecht
f5eeb5fa19 mac80211: fix invalid read in minstrel_sort_best_tp_rates()
At the last iteration of the loop, j may equal zero and thus
tp_list[j - 1] causes an invalid read.
Change the logic of the loop so that j - 1 is always >= 0.

Cc: stable@vger.kernel.org
Signed-off-by: Adrien Schildknecht <adrien+dev@schischi.me>
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
2015-08-13 13:52:34 +02:00
Thierry Reding
459cc2c680 drm/tegra: sor: Add HDMI support
The SOR1 introduced on Tegra210 supports HDMI 2.0 and DisplayPort. Add
HDMI support and name the debugfs node after the type of SOR. The SOR
introduced with Tegra124 is known simply as "sor", whereas the
additional SOR found on Tegra210 is known as "sor1".

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:49:37 +02:00
Thierry Reding
3309ac8362 drm/tegra: sor: Add Tegra210 eDP support
The SOR found on Tegra210 is very similar to the version found on
Tegra124, except that it no longer supports LVDS.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:49:36 +02:00
Thierry Reding
003fc84877 drm/tegra: dc: Implement atomic DPMS
Move all code into the new canonical ->disable() and ->enable() helper
callbacks so that they play extra nice with atomic DPMS.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:49:36 +02:00
Thierry Reding
850bab4480 drm/tegra: sor: Restore DPMS
In order to restore DPMS with atomic mode-setting, move all code from
the ->mode_set() callback into ->enable(). At the same time, rename the
->prepare() callback to ->disable() to use the names preferred by atomic
mode-setting. This simplifies the calling sequence and will allow DPMS
to use runtime PM in subsequent patches.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:49:35 +02:00
Thierry Reding
171e2e6dd9 drm/tegra: dsi: Restore DPMS
In order to restore DPMS with atomic mode-setting, move all code from
the ->mode_set() callback into ->enable(). At the same time, rename the
->prepare() callback to ->disable() to use the names preferred by atomic
mode-setting. This simplifies the calling sequence and will allow DPMS
to use runtime PM in subsequent patches.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:49:23 +02:00
Thierry Reding
29871b21c4 drm/tegra: hdmi: Restore DPMS
In order to restore DPMS with atomic mode-setting, move all code from
the ->mode_set() callback into ->enable(). At the same time, rename the
->prepare() callback to ->disable() to use the names preferred by atomic
mode-setting. This simplifies the calling sequence and will allow DPMS
code to use runtime PM in subsequent patches.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:49:11 +02:00
Thierry Reding
32c3dee11e drm/tegra: rgb: Restore DPMS
In order to restore DPMS with atomic mode-setting, move all code from
the ->mode_set() callback into ->enable(). At the same time, rename the
->prepare() callback to ->disable() to use the names preferred by atomic
mode-setting. This simplifies the calling sequence and will allow DPMS
code to use runtime PM in subsequent patches.

While at it, remove the enabled field that hasn't been used since the
demidlayering of the output drivers done in preparation for the atomic
mode-setting conversion.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:48:54 +02:00
Thierry Reding
530239a8b8 drm/tegra: sor: Use DRM debugfs infrastructure for CRC
Instead of duplicating most of the code to set up a debugfs file, use
the existing DRM core debugfs infrastructure instead.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:57 +02:00
Thierry Reding
51511d05de drm/tegra: sor: Write correct head state registers
The head state registers are per head, so they must be properly indexed.
This has worked fine so far because all boards with eDP use it as the
primary output, so it is very likely to end up attached to head 0.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:56 +02:00
Thierry Reding
8044449556 drm/tegra: sor: Constify display mode
The data structure is always only read, never written, and can hence be
referred to by a const pointer.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:56 +02:00
Thierry Reding
066d30f8c7 drm/tegra: sor: Reset the correct debugfs fields
When tearing down debugfs support, make sure to reset the fields to NULL
in the correct order, otherwise the debugfs root will not be properly
removed.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:55 +02:00
Thierry Reding
3ff1f22c88 drm/tegra: sor: Set minor after debugfs initialization
The DRM minor is needed to teardown debugfs, so it needs to be tracked
to prevent a crash on driver removal.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:53 +02:00
Thierry Reding
4dbdc740c4 drm/tegra: sor: Provide error messages in probe
When probing the SOR device fails, output proper error messages to help
diagnose the cause of the failure.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:51 +02:00
Thierry Reding
a9a9e4fd7c drm/tegra: sor: Rename registers for consistency
The TRM lists indexed registers without an underscore to separate name
from index. Use that convention in the driver for consistency.

While at it, rename some of the field names to the names used in the
TRM.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:50 +02:00
Thierry Reding
9e532b3ad9 drm/tegra: dpaux: Disable interrupt when detached
When the DPAUX isn't attached to an SOR the interrupts are not useful.
This also prevents a race that could potentially cause a crash on driver
removal.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:49 +02:00
Thierry Reding
3227166c3b drm/tegra: dpaux: Configure pads as I2C by default
The DPAUX code paths already configure the pads in AUX mode, but there
is no way to reconfigure them in I2C mode for HDMI (the DPAUX module is
unused in that case). Enabling the pads in I2C mode by default is the
quickest way to support HDMI. Eventually this may need an explicit call
in the user drivers.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:47 +02:00
Thierry Reding
08f580ef2f drm/tegra: dpaux: Provide error message in probe
When probing the dpaux device fails, output proper error messages to
help diagnose the cause of the failure.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:46 +02:00
Thierry Reding
ddfb406b2f drm/tegra: dsi: Add Tegra210 support
The DSI host controller hasn't changed from Tegra132 to Tegra210, but
different characterization parameters may be required.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:45 +02:00
Thierry Reding
c06c793084 drm/tegra: dsi: Add Tegra132 support
The DSI host controller hasn't changed from Tegra124 to Tegra132, but
different characterization parameters may be required.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:44 +02:00
Thierry Reding
7d3385875b drm/tegra: dsi: Add Tegra124 support
The DSI host controller hasn't changed from Tegra114 to Tegra124, but
different characterization parameters may be required.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:44 +02:00
Thierry Reding
b8be0bdbd5 drm/tegra: dsi: Use proper back-porch for non-sync video mode
In video modes without sync pulses, the horizontal back-porch needs to
include the horizontal sync width.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:44 +02:00
Thierry Reding
472a6d1fd5 drm/tegra: dc: Rename BASE_COLOR_SIZE* fields
Use an underscore to separate the prefix from the color size suffix.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:43 +02:00
Thierry Reding
76ac3284bb drm/tegra: dc: Don't explicitly set owner module
The call to platform_driver_register() will already set up the .owner
field, so there's no need to do it explicitly.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:43 +02:00
Thierry Reding
8fd3ffa902 drm/tegra: dc: Rename register for consistency
The horizontal pulse enable bits are named H_PULSE{0,1,2}_ENABLE in the
TRM. Modify the driver to use the same naming for consistency.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:43 +02:00
Thierry Reding
791ddb1e1c drm/tegra: dc: Record statistics
Record interrupt statistics, such as the number of frames and VBLANKs
received and the number of FIFO underflow and overflows.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:43 +02:00
Thierry Reding
01a5da0c10 drm/tegra: dc: Request syncpoint earlier
Request a syncpoint for display prior to registering the host1x client.
This will ensure that the syncpoint will be acquired when the KMS driver
initializes.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:42 +02:00
Thierry Reding
e83dcb5bb6 drm/tegra: dc: Remove gratuituous blank line
Blank lines at the end of functions are hideous, so get rid of it.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:42 +02:00
Thierry Reding
a1df3b2488 drm/tegra: dc: Clarify comment about cursor treatment
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:42 +02:00
Thierry Reding
6ca1f62f0d drm/tegra: dc: Implement CRC debugfs interface
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:41 +02:00
Thierry Reding
5b4f516f5c drm/tegra: dc: Add Tegra210 support
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:41 +02:00
Thierry Reding
31930d4d08 drm/tegra: dc: Reset VBLANK to off
Upon driver load, reset the VBLANK machinery to off to reflect the
hardware state. Since the ->reset() callback is called from the initial
drm_mode_config_reset() call, move the latter after the VBLANK machinery
initialization by drm_vblank_init().

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:40 +02:00
Thierry Reding
fb36d0eed4 drm/tegra: output: Support low-active hotplug detect
Support low-active hotplug detect signals by storing the GPIO flags
parsed from device tree.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:40 +02:00
Thierry Reding
a13f1dc4c3 drm/tegra: Use SIMPLE_DEV_PM_OPS
Use this macro to reduce some of the boilerplate.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:24 +02:00
Thierry Reding
cdc630b6c6 drm/tegra: Allow VBLANK to be disabled
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:22 +02:00
Thierry Reding
15372d4be7 gpu: host1x: mipi: Power down regulators when unused
Keep track of the number of users of DSI and CSI pads and power down the
regulators that supply the bricks when all users are gone.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:21 +02:00
Thierry Reding
5e7752436e gpu: host1x: mipi: Add Tegra210 support
Some changes are needed to the configuration settings for some lanes. In
addition, the clock lanes for the CSI pads can no longer be calibrated.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:20 +02:00
Thierry Reding
7fd3ecad3f gpu: host1x: mipi: Add Tegra132 support
While Tegra132 has the same pads as Tegra124, some configuration values
need to be programmed slightly differently.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:19 +02:00
Thierry Reding
c22fb79099 gpu: host1x: mipi: Constify OF match table
This table is never modified and can therefore reside in read-only
memory.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:18 +02:00
Thierry Reding
2ed264bf91 gpu: host1x: mipi: Clear calibration status
Before starting a new calibration cycle, make sure to clear the current
status by writing a 1 to the various "calibration done" bits.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:17 +02:00
Thierry Reding
8ed5c06232 gpu: host1x: mipi: Fix clock lane register for DSI
Use more consistent names for the clock lane configuration registers and
fix the offset of the upper clock lane configuration register for the
first DSI pad.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:16 +02:00
Thierry Reding
83a3c223cc gpu: host1x: mipi: Parameterize to support future SoCs
Parameterize more of the register programming to accomodate for changes
required by future SoC generations.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:15 +02:00
Olof Johansson
db55350599 The i.MX fixes for 4.2, 3rd round:
- Fix i.MX6 PCIe interrupt routing which gets missed from stacked IRQ
    domain conversion.  The PCIe wakeup support is currently broken
    because of this.
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Merge tag 'imx-fixes-4.2-3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into fixes

The i.MX fixes for 4.2, 3rd round:
 - Fix i.MX6 PCIe interrupt routing which gets missed from stacked IRQ
   domain conversion.  The PCIe wakeup support is currently broken
   because of this.

* tag 'imx-fixes-4.2-3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  ARM: imx6: correct i.MX6 PCIe interrupt routing

Signed-off-by: Olof Johansson <olof@lixom.net>
2015-08-13 12:24:55 +02:00
Olof Johansson
07616f013b Two fixes for bugs in Exynos power domain error exit path:
1. kfree() of read-only memory (name of power domain returned
    by kstrdup_const()),
 2. Doubled of_node_put() leading to invalid ref count for OF node.
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Merge tag 'samsung-mach-fixes-4.2' of https://github.com/krzk/linux into fixes

Two fixes for bugs in Exynos power domain error exit path:
1. kfree() of read-only memory (name of power domain returned
   by kstrdup_const()),
2. Doubled of_node_put() leading to invalid ref count for OF node.

* tag 'samsung-mach-fixes-4.2' of https://github.com/krzk/linux:
  ARM: EXYNOS: fix double of_node_put() on error path
  ARM: EXYNOS: Fix potentian kfree() of ro memory

Signed-off-by: Olof Johansson <olof@lixom.net>
2015-08-13 12:18:45 +02:00
Maarten Lankhorst
d2944cf213 drm/i915: Commit planes on each crtc separately.
This patch is based on the upstream commit 5ac1c4bcf0 and amended
for v4.2 to make sure it works as intended.

Repeated calls to begin_crtc_commit can cause warnings like this:
[  169.127746] BUG: sleeping function called from invalid context at kernel/locking/mutex.c:616
[  169.127835] in_atomic(): 0, irqs_disabled(): 1, pid: 1947, name: kms_flip
[  169.127840] 3 locks held by kms_flip/1947:
[  169.127843]  #0:  (&dev->mode_config.mutex){+.+.+.}, at: [<ffffffff814774bc>] __drm_modeset_lock_all+0x9c/0x130
[  169.127860]  #1:  (crtc_ww_class_acquire){+.+.+.}, at: [<ffffffff814774cd>] __drm_modeset_lock_all+0xad/0x130
[  169.127870]  #2:  (crtc_ww_class_mutex){+.+.+.}, at: [<ffffffff81477178>] drm_modeset_lock+0x38/0x110
[  169.127879] irq event stamp: 665690
[  169.127882] hardirqs last  enabled at (665689): [<ffffffff817ffdb5>] _raw_spin_unlock_irqrestore+0x55/0x70
[  169.127889] hardirqs last disabled at (665690): [<ffffffffc0197a23>] intel_pipe_update_start+0x113/0x5c0 [i915]
[  169.127936] softirqs last  enabled at (665470): [<ffffffff8108a766>] __do_softirq+0x236/0x650
[  169.127942] softirqs last disabled at (665465): [<ffffffff8108ae75>] irq_exit+0xc5/0xd0
[  169.127951] CPU: 1 PID: 1947 Comm: kms_flip Not tainted 4.1.0-rc4-patser+ #4039
[  169.127954] Hardware name: LENOVO 2349AV8/2349AV8, BIOS G1ETA5WW (2.65 ) 04/15/2014
[  169.127957]  ffff8800c49036f0 ffff8800cde5fa28 ffffffff817f6907 0000000080000001
[  169.127964]  0000000000000000 ffff8800cde5fa58 ffffffff810aebed 0000000000000046
[  169.127970]  ffffffff81c5d518 0000000000000268 0000000000000000 ffff8800cde5fa88
[  169.127981] Call Trace:
[  169.127992]  [<ffffffff817f6907>] dump_stack+0x4f/0x7b
[  169.128001]  [<ffffffff810aebed>] ___might_sleep+0x16d/0x270
[  169.128008]  [<ffffffff810aed38>] __might_sleep+0x48/0x90
[  169.128017]  [<ffffffff817fc359>] mutex_lock_nested+0x29/0x410
[  169.128073]  [<ffffffffc01635f0>] ? vgpu_write64+0x220/0x220 [i915]
[  169.128138]  [<ffffffffc017fddf>] ? ironlake_update_primary_plane+0x2ff/0x410 [i915]
[  169.128198]  [<ffffffffc0190e75>] intel_frontbuffer_flush+0x25/0x70 [i915]
[  169.128253]  [<ffffffffc01831ac>] intel_finish_crtc_commit+0x4c/0x180 [i915]
[  169.128279]  [<ffffffffc00784ac>] drm_atomic_helper_commit_planes+0x12c/0x240 [drm_kms_helper]
[  169.128338]  [<ffffffffc0184264>] __intel_set_mode+0x684/0x830 [i915]
[  169.128378]  [<ffffffffc018a84a>] intel_crtc_set_config+0x49a/0x620 [i915]
[  169.128385]  [<ffffffff817fdd39>] ? mutex_unlock+0x9/0x10
[  169.128391]  [<ffffffff81467b69>] drm_mode_set_config_internal+0x69/0x120
[  169.128398]  [<ffffffff8119b547>] ? might_fault+0x57/0xb0
[  169.128403]  [<ffffffff8146bf93>] drm_mode_setcrtc+0x253/0x620
[  169.128409]  [<ffffffff8145c600>] drm_ioctl+0x1a0/0x6a0
[  169.128415]  [<ffffffff810b3b41>] ? get_parent_ip+0x11/0x50
[  169.128424]  [<ffffffff811e9ab8>] do_vfs_ioctl+0x2f8/0x530
[  169.128429]  [<ffffffff810d0fcd>] ? trace_hardirqs_on+0xd/0x10
[  169.128435]  [<ffffffff812e7676>] ? selinux_file_ioctl+0x56/0x100
[  169.128439]  [<ffffffff811e9d71>] SyS_ioctl+0x81/0xa0
[  169.128445]  [<ffffffff81800697>] system_call_fastpath+0x12/0x6f

Solve it by using the newly introduced drm_atomic_helper_commit_planes_on_crtc.

The problem here was that the drm_atomic_helper_commit_planes() helper
we were using was basically designed to do

    begin_crtc_commit(crtc #1)
    begin_crtc_commit(crtc #2)
    ...
    commit all planes
    finish_crtc_commit(crtc #1)
    finish_crtc_commit(crtc #2)

The problem here is that since our hardware relies on vblank evasion,
our CRTC 'begin' function waits until we're out of the danger zone in
which register writes might wind up straddling the vblank, then disables
interrupts; our 'finish' function re-enables interrupts after the
registers have been written.  The expectation is that the operations between
'begin' and 'end' must be performed without sleeping (since interrupts
are disabled) and should happen as quickly as possible.  By clumping all
of the 'begin' calls together, we introducing a couple problems:
 * Subsequent 'begin' invocations might sleep (which is illegal)
 * The first 'begin' ensured that we were far enough from the vblank that
   we could write our registers safely and ensure they all fell within
   the same frame.  Adding extra delay waiting for subsequent CRTC's
   wasn't accounted for and could put us back into the 'danger zone' for
   CRTC #1.

This commit solves the problem by using a new helper that allows an
order of operations like:

   for each crtc {
        begin_crtc_commit(crtc)  // sleep (maybe), then disable interrupts
        commit planes for this specific CRTC
        end_crtc_commit(crtc)    // reenable interrupts
   }

so that sleeps will only be performed while interrupts are enabled and
we can be sure that registers for a CRTC will be written immediately
once we know we're in the safe zone.

The crtc->config->base.crtc update may seem unrelated, but the helper
will use it to obtain the crtc for the state. Without the update it
will dereference NULL and crash.

Changes since v1:
- Use Matt Roper's commit message.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
References: https://bugs.freedesktop.org/show_bug.cgi?id=90398
Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2015-08-13 12:09:18 +03:00
Maarten Lankhorst
f0fdc55db0 drm/i915: calculate primary visibility changes instead of calling from set_config
This should be much cleaner, with the same effects.

(cherry picked for v4.2 from commit fb9d6cf8c2)
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
References: https://bugs.freedesktop.org/show_bug.cgi?id=90398
Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2015-08-13 12:08:47 +03:00
Daniel Vetter
e8fa427053 drm/i915: Only dither on 6bpc panels
In

commit d328c9d78d
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date:   Fri Apr 10 16:22:37 2015 +0200

    drm/i915: Select starting pipe bpp irrespective or the primary plane

we started to select the pipe bpp from sink capabilities and not from
the primary framebuffer - that one might change (and we don't want to
incur a modeset) and sprites might contain higher bpp content too.

We also selected dithering on a 8 bpc screen displaying a 24bpp rgb
primary, because pipe_bpp is 24 for such a typical 8 bpc sink, but since
the commit mentioned above, base_bpp is always the absolute maximum
supported by the hardware, e.g., 36 bpp on my Ironlake chip. Iow. the
only way to not get dithering would have been to connect a deep color 12
bpc display, so pipe_bpp == 36 == base_bpp.

Hence only enable dithering on 6bpc screens where we difinitely and
always want it.

Cc: Mario Kleiner <mario.kleiner.de@gmail.com>
Reported-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Reviewed-and-tested-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2015-08-13 11:31:56 +03:00
Horia Geant?
b310c178e6 crypto: caam - fix memory corruption in ahash_final_ctx
When doing pointer operation for accessing the HW S/G table,
a value representing number of entries (and not number of bytes)
must be used.

Cc: <stable@vger.kernel.org> # 3.6+
Fixes: 045e36780f ("crypto: caam - ahash hmac support")
Signed-off-by: Horia Geant? <horia.geanta@freescale.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-08-13 15:08:25 +08:00
Woodrow Shen
7ccb0a9917 ALSA: hda - Fix the white noise on Dell laptop
Dell laptop causes the white noise by login screen and headphone,
and the fixup function ALC292_FIXUP_DISABLE_AAMIX can eliminate this
noise.

Codec: Realtek ALC3235
Vendor Id: 0x10ec0293
Subsystem Id: 0x102806db

Cc: <stable@vger.kernel.org>
BugLink: https://bugs.launchpad.net/bugs/1484334
Signed-off-by: Woodrow Shen <woodrow.shen@canonical.com>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2015-08-13 07:56:44 +02:00
Michael Walle
5c16179b55 EDAC, ppc4xx: Access mci->csrows array elements properly
The commit

  de3910eb79 ("edac: change the mem allocation scheme to
		 make Documentation/kobject.txt happy")

changed the memory allocation for the csrows member. But ppc4xx_edac was
forgotten in the patch. Fix it.

Signed-off-by: Michael Walle <michael@walle.cc>
Cc: <stable@vger.kernel.org>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
Link: http://lkml.kernel.org/r/1437469253-8611-1-git-send-email-michael@walle.cc
Signed-off-by: Borislav Petkov <bp@suse.de>
2015-08-13 06:02:19 +02:00