The current api which performs the clock reset is moved to use the reset
framework, so support the changes in USB driver for the same. The reset
framework requires to get reset handle and perform assert/deassert of the
resets.
Change-Id: Ifcde1c6af624294cbd1944eaa9b526dd6dcc51de
Signed-off-by: Amit Nischal <anischal@codeaurora.org>
Read the charger die temperature and its threshold from RR_ADC,
and expose to the userspace through battery PSY.
Read USBIN current and voltage from RR_ADC, and expose to the
userspace through USB PSY.
CRs-Fixed: 1050042
Change-Id: I452a050298a6ab081f64aa2dcf295d2d257bcb32
Signed-off-by: Harry Yang <harryy@codeaurora.org>
Add support for ARCH_MSMTRITON in msmfalcon arm64
defconfigs.
Change-Id: Ic83fe1607d5f62e0ceefd4497aae0c111a2727d7
Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org>
Add device tree files necessary to support msmtriton SoC.
Also, add support for Rumi platform.
Change-Id: Ia18a2f53fc3bf7ca459182dc197ad6a2078c7f5c
Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org>
Use the no-log variants of the read{b,q,l}/write{b,q,l} APIs
to prevent flooding the MSM register trace buffer (RTB) logs
with memcpy/memset induced logging.
Change-Id: I16556e1d6f4abe00e6f33b8375a5a1839dfca34e
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
Add the VDD_APC CPR corner configuration corresponding to
speed-bin 1 parts whose performance cluster can operate
at a slower maximum clock rate compared to speed-bin 0 parts.
CRs-Fixed: 1057119
Change-Id: I01e2c9c8bafbb2be4c8d312a4212195c2a99f3ac
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Update VDD_APC0 and VDD_APC1 CPR floor and ceiling voltages
of the highest fused corner on msmcobalt v2 parts to
adhere to latest hardware guidelines.
CRs-Fixed: 1057119
Change-Id: Icf06fe334558bfc4e4dedc9b1f18d51c99987966
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Add support for msmcobalt speed-bin 1 devices which can operate
with a performance cluster clock frequency of up to 2.208 GHz.
CRs-Fixed: 1057115
Change-Id: I2c733a1f0ee4baf978c3715aa3bd74a6b46ee6c2
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
On MSMCOBALT, the GPU GX GDSC enable status register must be
polled to see if the GPU (and top level CPR sensors) are powered
before attempting to perform a CPR aging measurement.
Specify the address of this register as well the bitmask and
expected enable state masked register value in the VDD_GFX CPR
device node.
Change-Id: I55d5fb0c799dfec73830e8e97dcff79cd045b29c
Signed-off-by: David Collins <collinsd@codeaurora.org>
1. Select COMMON_CLK_MSM for msmfalcon when building
for 32-bit.
2. Select RATIONAL when COMMON_CLK_MSM is selected as
it's using an api from rational library.
Change-Id: I5b8fa962718a5ae44dfd18a13285715580ee0dbc
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
As per the new schematic the debug uart is on BLSP1UART1
instead of BLSP2UART1.
Change-Id: I08b3ffa1a027b3212b77fe661348f2852485ed0d
Signed-off-by: Venkatesh Yadav Abbarapu <vabbar@codeaurora.org>
Audio codec now supports audio both on HDMI and display port
interfaces. Rename audio codec and compatible string to be
generic.
Change-Id: I7c2ace6dedc0cad34fe0ab46c6290526972824a1
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Update the initial VDD_GFX CPR step quotient values to match the
latest hardware recommendation.
Change-Id: Ibc5da9bb1e47e32acb0268a15cea79d48907b106
CRs-Fixed: 1054539
Signed-off-by: David Collins <collinsd@codeaurora.org>
Add initial device trees for msmcobalt QRD VR1 board.
Change-Id: I94ebf6366b75daf9102a50eb86e757139e6d4231
Signed-off-by: Xiaogang Cui <xiaogang@codeaurora.org>
Hardware characterization has shown that some parts require
higher voltage in order to operate reliably. Therefore, raise
the CPR ceiling voltages for the VDD_GFX CPR regulator in order
to allow higher open-loop voltages.
Change-Id: I8c4ceaa2703c15c1f590befb9397d47da9f9c1e9
CRs-Fixed: 1054539
Signed-off-by: David Collins <collinsd@codeaurora.org>
Efuse parameters are used to update qusb analog tuning values.
Change-Id: I4bc919ba7cf24d73cbc6cac392e00f81005bf64c
Signed-off-by: Vamsi Krishna Samavedam <vskrishn@codeaurora.org>
Update the sequence to include tune1 and tune2 parameters. While
at it update the comments to include register names.
Change-Id: Ib8ff42a6e05c0065b19e977eb56f6b96a78fcf39
Signed-off-by: Vamsi Krishna Samavedam <vskrishn@codeaurora.org>
Update the tcsr_clamp_dig_n signal and phy init sequence
to reduce the random leakage from qusb2 phy. Random leakage
can result from turning on/off analog power rails
before/after digital power rails.
Change-Id: Id51a2d34f61c0a41891551d15b706872abf13809
Signed-off-by: Vamsi Krishna Samavedam <vskrishn@codeaurora.org>
