Define the open-loop and closed-loop fused corner voltage
margin adjustments for CPR local rev >= 1 parts. This ensures
the CPU clusters powered by VDD_APC0 and VDD_APC1 rails on
CPR rev >= 1 msmcobalt chips have sufficient voltage margin
for stable operation.
CRs-Fixed: 1030441
Change-Id: I3d9cf9179c78619933c11d966ae19a8851749595
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Enabling the configuration for qtaguid which is needed for
enabling bandwidth control from userspace.
Change-Id: I5d0fe18bbef5b80085a9cd77f49eb77e3c654542
CRs-Fixed: 1030408
Signed-off-by: Bryse Flowers <bflowers@codeaurora.org>
Changes to support MIPI Cphy mode on CSID version 5.0.
CRs-Fixed: 1030317
Change-Id: I6e0835811a47820714eddcf851ea15ece729c2bb
Signed-off-by: Viswanadha Raju Thotakura <viswanad@codeaurora.org>
Add support for the mdss_mdp_lut_clk clock on MSMCOBALT.
In addition, remove toggling the memory retention bits for the
mdp core clock during gdsc_enable/disable. The display driver
will use the set_flags API to set the core clock memory retention.
CRs-Fixed: 1025605
Change-Id: If812473a67a7900c8f7b8b97f32fbf003f0e80a4
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Starting with DSI PHY hardware revisions 3.0 and above, data lane swap
configurations need to be programmed via the DSI PHY interface. In other
cases, a new register interface has been introduced to program the lane
swap configuration for DSI controller revision 2.0 and above. Refactor
the existing implementation to account for these hardware changes.
Change-Id: I3772c614bfee0ed13f30a38535bb814158d23226
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Add code to allocate memory for dumping TMC register and buffer data.
These memory locations can be used to store TMC registers and buffer
information after a crash.
Change-Id: I8e98178110efa8e455a329e358c471757e87f2d1
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
DSB_TIER.PATT_TYPE bit can be used to choose a driver for
pattern matching based timestamps for DSB subunit.
Add support to configure this bit.
Change-Id: Id07ee18006c96e9a66cab5f4e7544dda85a692f8
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
The IBB pulse-skip and NLIMIT DAC configuration should be disabled
before applying the 2nd SWIRE command skip logic, to guarantee
that the IBB voltage changes immediately in the subsequent
SWIRE command. After the WA is completed, the pulse-skip can
be re-enabled after a programmable delay. Add this logic and
a DT property 'qcom,swire-ibb-ps-enable-delay' to configure
this delay. If this delay is not specified in the DT it defaults
to 200ms.
CRs-Fixed: 1010085
Change-Id: Ifec458a0028c16440ffd6ac1f6fa58eebc815c5a
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. For CPUfreq
purposes probe these devices and expose a mux clock that chooses
between PXO and PLL8.
Change-Id: Icaa1b68652eb4c836e8aacad80ff6cebe34cad4f
Cc: <devicetree@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
The Krait clocks are made up of a series of muxes and a divider
that choose between a fixed rate clock and dedicated HFPLLs for
each CPU. Instead of using mmio accesses to remux parents, the
Krait implementation exposes the remux control via cp15
registers. Support these clocks.
Change-Id: Ic720d45d8c78e6c5a901e58ec6fd23fa15302a21
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
HFPLLs are the main frequency source for Krait CPU clocks. Add
support for changing the rate of these PLLs.
Change-Id: I53cb4364e84d108f4fc211ca5524ca25d569997c
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
On some devices (MSM8974 for example), the HFPLLs are
instantiated within the Krait processor subsystem as separate
register regions. Add a driver for these PLLs so that we can
provide HFPLL clocks for use by the system.
Change-Id: If8a3e492e1c227cbf42f4f9907cdcb0dcb3ccc11
Cc: <devicetree@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
We can't control eSE power through driver as of now
so adding gpio pin support for eSE in NQxxx driver.
Multiline comments are updated.
Change-Id: I60651052d7bf97a8a0505e76904cebe2b7c69ce2
Signed-off-by: Gaurav Singhal <gsinghal@codeaurora.org>
In the current implementation N_MULTIPLIER bit for audio packets
on HDMI TX controller is not getting set properly. Fix this issue
by setting the multiplier value according to the sample rate set
for audio playback.
Change-Id: I25ab63eeadd5fd08649e9e828dcab83ec1b60161
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
Rename wcd-gpio-ctrl to msm-cdc-pinctrl as these
changes are not wcd specific.
CRs-fixed: 1028800
Change-Id: Iffc36dd27ae3b651b736acab004d6fff3bdcb2c7
Signed-off-by: Yeleswarapu Nagaradhesh <nagaradh@codeaurora.org>
Enable FD for msmcobalt in dtsi.
CRs-Fixed: 1030317
Change-Id: Ie82b62777d0a5c5610b985a42dbe14ce54acb006
Signed-off-by: JinHee Kim <jinheek@codeaurora.org>
Enable SMB138X parallel charger device support for the msmcobalt platform.
CRs-Fixed: 1023141
Change-Id: Ifb806bb4c18a9d1c0c1357fef1600d1bc67c149f
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
Add the SMB138X parallel charger device that is present in msmcobalt-mtp
CRs-Fixed: 1023141
Change-Id: Iba87437d7d57f4f42f973ea7db2af5ff8b579bd3
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
This driver supports the SMB138X charger device.
This charger peripheral is common among other chips, therefore the
driver uses the smb library to support all common functionality.
Register access is provided by the parent device via regmap. Interrupts
are controlled by the parent device, and handlers are registered by the
SMB138X charger driver.
The power supply framework is used to communicate battery and usb
properties to userspace and other driver consumers such as fuel gauge
and USB.
VBUS and VCONN regulators are registered for supporting OTG, and powered
Type-C cables respectively.
CRs-Fixed: 1023141
Change-Id: I119d33cdfdfc874b5d7f6137618ee3e590c72064
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
Add BIMC gdsc data found in MMCC part of msm8996 family of devices.
Change-Id: Ibeac134f941f402bcad8e803bdb73ba73f55909d
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Add all gdsc data which are part of mmcc on msm8996 family
Change-Id: I77caf8f26bf676a7553b6873eb188acb02a9c44d
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Add a driver for the multimedia clock controller found on MSM8996
based devices. This should allow most multimedia device drivers
to probe and control their clocks.
Change-Id: I0b69b1e78a8b0faeaff3e5c87c73e24b1c19ba55
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
Add icl handler to report USB input current limit, and charge handler
to report charging state changes, providing input to parallel
charging algorithm.
CRs-Fixed: 1023703
Change-Id: Id51ad3dbd6e2637c105db681082eea98ab161a50
Signed-off-by: Harry Yang <harryy@codeaurora.org>
mnoc_ahb clock should be enabled prior to enabling the mdss_ahb
clock for any register access in the HDMI domain.
CRs-Fixed: 1022772
Change-Id: If78feebe1efb3efa2490551374a35ea702496323
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Handle CEC interrupts in the CEC hardware module only if the CEC
feature is explicitly enabled by the CEC framework. This will
prevent the CEC hardware module from unnecessarily processing
interrupts that will not be handled by the CEC framework (if
the feature is not explicity enabled).
Change-Id: I5110f2c8277581f87da71f962560c33f65582176
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
CRs-Fixed: 1016853
Add a votable structure - one veto to disable or unanimous
approval to enable.
Provide an open and flexiable machanism to enable/disable
parallel charging based on various dynamically changing
factors.
CRs-Fixed: 1023703
Change-Id: I552467645d6f8f633afe273b173a636e0eb396a7
Signed-off-by: Harry Yang <harryy@codeaurora.org>
Implement wake votable on top of PM wakesource APIs for PMIC voters
to hold system awake.
CRs-Fixed: 1023703
Change-Id: If2c8f65d932f2f0bdad9f0f026d440a2089cec5f
Signed-off-by: Harry Yang <harryy@codeaurora.org>
IPA FWs load should use CMA memory as intermediate memory
for loading the FWs instead of the peripheral memory.
Change-Id: I0f7e8af9d233390861972048b07cc02dfaf1ed14
CRs-Fixed: 1025417
Signed-off-by: Ghanim Fodi <gfodi@codeaurora.org>
Add pointer validation checks to prevent sending
invalid handles to ADSP as part of unmap memory
regions command.
CRs-Fixed: 1018367
Change-Id: I0dfb2fccb4414ed82ee10d73576fda66a273043d
Signed-off-by: Karthik Reddy Katta <a_katta@codeaurora.org>
MMMS mnoc_ahb clock needs to be enabled prior to enabling the
mdss_ahb clock on msmcobalt as there is a core fsm dependency
between these clocks.
CRs-Fixed: 1022772
Change-Id: I24f3b01ae40d1242e64bfc87177142b0d64ac123
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
The block reset registers for USB3 and PCIE will be required by the clients
to reset their subsystem blocks so add them in the reset map.
Change-Id: Ie30158592fca057454152f3f46a5d8b89ae36b88
Signed-off-by: Amit Nischal <anischal@codeaurora.org>
offset_entry parameter should be tested for NULL, invert
testing logic.
CRs-Fixed: 1028328
Change-Id: I52761b04c594b10202a3823d49324a4991ecf3e4
Signed-off-by: Amir Levy <alevy@codeaurora.org>
Without 'coresight-name' a CoreSight device gets registered with its
dev_name.
This can be a problem in case where we have CoreSight properties defined
within some other platform device.
Make 'coresight-name' a required property for a CoreSight device to
avoid this problem.
Change-Id: I5e192c4d850bb040983024cfe163714fbebbb199
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
With GRO enable, ipa3 still use default
aggr_byte_limit to calculates the
rx_buff_sz and configures wrong channel
righ size in GSI. The fix is to use
the right aggr_byte_limit which netmgrd
configured.
Change-Id: I9f804a122090ea4340f7873a5aa276dff00cbcb7
Signed-off-by: Skylar Chang <chiaweic@codeaurora.org>
On MSMCOBALT, the votable GDSCs might take longer to enable/disable
depending on a number of factors including if another entity outside
of HLOS tried disabling the GDSC at the same time that HLOS tried to
enable it. Add a higher polling timeout to accommodate this.
In addition, add flags to branch clocks which might be controlled via
the voting registers so that the driver does not print out a warning
if these clocks do not turn off even after removing the SW vote.
CRs-Fixed: 1027807
Change-Id: I044ca5209c364d4bfb4f3bd504cdcb87021fd010
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Add codec reset gpio device tree node for msmcobalt target
specifying active and sleep pinctrl states.
CRs-fixed: 1028800
Change-Id: Id2625cd71b4c204ce10bc6dd007939834d2b9e10
Signed-off-by: Phani Kumar Uppalapati <phaniu@codeaurora.org>
If usb_ep_queue() fails on queueing zero-length packet, driver is not
decrementing dpkts_tolaptop_pending counter which may results into seeing
count mismatch. Hence decrement dpkts_tolaptop_pending if zero length
packet queueing fails.
CRs-Fixed: 1027031
Change-Id: Id3c7c2627bdf37524067512db51d3180c570106d
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
Currently driver is reading and logging usage count of gadget
device but it is required to use usage count of gadget's parent
device which is used to prevent USB controller's low power mode.
Hence fix reporting of USB devices' usage count.
Also mark sm_state to initialized and remove queueing of
ipa_usb_wq as ipa_work_handler() is running without USB gadget
is initialized i.e. gadget is NULL.
CRs-Fixed: 1021499
Change-Id: Ia64afa3adb769674f6a9a60fde2c7397b7e4fe49
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
When smd_trans is registered at bootup and the transport
field is null, glink_pkt gets a link up notification early.
Use the requested transport to register for the link up
notification of the edge.
CRs-Fixed: 1028203
Change-Id: I8f549a48efe19f66e3a336a21b75903f7800ed86
Signed-off-by: Chris Lew <clew@codeaurora.org>
Remove the no-map and shared-dma-pool properties for dynamic fps
memory node. The DSI PLL driver allocates virtual memory space to
ioremap the reserved memory pages to it. The DSI PLL codes are
then copied from this virtual memory.
Change-Id: If65b653137b5c0f69fb66d77389bd71e6c3a0259
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
DSI controller requests for PM_QOS while sending DCS commands, so
that CPU does not go to idle state until DCS command transfer is
finished. But this request can come independently from multiple
clients such as different DSI controllers. So this change adds
ref count based PM_QOS request to avoid warning for multiple QOS
add request and unwanted results, if one client removes the request
while the other clients still need it.
Change-Id: If3ca0161923fcd73fdde77984aa5d80bfaec79a1
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
Camera daemon process is moving to mediaserver
process. MCT will send contol command
to indicate camera daemon is present or not.
For backward compatibility, add check
so kernel can support camera daemon present
and camera daemon not present.
Change-Id: Ia9e45f539bd5ec0d2edfe9bfb90942d88b6d30da
Signed-off-by: Jignesh Mehta <jigneshm@codeaurora.org>
Clearing Non uC interrupts before processing will
result in clearing interrupt data.
Change-Id: I47ea7c22250264da206e1fb8691e77224c825ab0
CRs-Fixed: 1008549
Signed-off-by: sunil paidimarri <hisunil@codeaurora.org>
We have scripts which write to certain fields on 3.18 kernels but
this seems to be failing on 4.4 kernels.
An entry which we write to here is xfrm_aevent_rseqth which is u32.
echo 4294967295 > /proc/sys/net/core/xfrm_aevent_rseqth
Commit 230633d109 ("kernel/sysctl.c:
detect overflows when converting to int") prevented writing to
sysctl entries when integer overflow occurs. However, this does not
apply to unsigned integers.
u32 should be able to hold 4294967295 here, however it fails due to
this check.
static int do_proc_dointvec_conv(bool *negp, unsigned long *lvalp,
if (*lvalp > (unsigned long) INT_MAX)
return -EINVAL;
Fix this for now by reverting this commit till a solution is
finalized upstream.
CRs-Fixed: 1026507
Change-Id: I4fae5f442e4cc2c2414a69e960d42c05c3062415
Signed-off-by: Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>
generalise ARCH_QCOM platform to support new 32-bit
qcom platforms.
Change-Id: I412a83a2f756b02d6b521983501de780835dc118
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
The boot/dts/Makefile and boot/dts/*/Makefile provide DTB_LIST which is
equal to dtb-y when CONFIG_BUILD_ARM_APPENDED_DTB_IMAGE=y.
Include these Makefiles to build dtbs for dtb appended zImage.
Change-Id: Ib8218135dc923d1ba4098d74dbd7da159368a188
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
[abhimany: resolve trivial merge conflict]
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
[sramana: Fixed merge conflicts]
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
Add the dts files to the compilation target when compiling
for arm.
Change-Id: I3146989f6e73bfe101ac9363428bd0beecd09c32
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
