The global struct list_head pchannels should be directly
used as the list head for pchan list traversal. Previously,
a local struct list_head instance was wrongly created and
used for such traversal. It caused kernel panic in system
shutdown.
Change-Id: Ifb82b55d5a0237fd12f8f53db095fccbcef96fb8
Signed-off-by: Yong Ding <yongding@codeaurora.org>
Mizar board doesn't have rh850 can controller
Change-Id: Ie3eb224fc4dfa71da7d290bfaf47ae4b9fcaceb4
Signed-off-by: Alex Yakavenka <ayakav@codeaurora.org>
This change add check to existing vblank request state. It will avoid
enable vblank multiple times. It will also avoid disable vblank
multiple times.
Change-Id: I10781c33e51b1032b72fcbc1a01a7d01be8be510
Signed-off-by: Camus Wong <camusw@codeaurora.org>
Send context ID in rpc header instead of context pointer.
Validate context ID received in response and get context pointer.
Change-Id: I9cfd10d0c1b25c3085b8e15c7ca1c8ff214bf10d
Acked-by: Viswanatham Paduchuri <vpaduchu@qti.qualcomm.com>
Signed-off-by: Tharun Kumar Merugu <mtharu@codeaurora.org>
We call arm64_apply_bp_hardening() from post_ttbr_update_workaround,
which has the unexpected consequence of being triggered on every
exception return to userspace when ARM64_SW_TTBR0_PAN is selected,
even if no context switch actually occured.
This is a bit suboptimal, and it would be more logical to only
invalidate the branch predictor when we actually switch to
a different mm.
In order to solve this, move the call to arm64_apply_bp_hardening()
into check_and_switch_context(), where we're guaranteed to pick
a different mm context.
Change-Id: I28f2fb09b77544e5ead095e9dad1ad64b2b3ae36
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Git-commit: a8e4c0a919ae310944ed2c9ace11cf3ccd8a609b
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
Kryo cores are exposed to two vulnerabilities due to subroutine return
(called LINK-STACK) and branch target predictors.
These two issues can be mitigated through software workarounds.
Kernel:
- Apply LINK-STACK mitigation which is to issue 16 nested BL instructions
on process context switch 'cpu_do_switch_mm()' where ASID changes.
- Apply psci based branch predictor invalidation.
use the kryo core detection routine (based on MIDR) from the
commit bb48711800e6d ("arm64: cpu_errata: Add Kryo to Falkor 1003 errata")
by Stephen Boyd <sboyd@codeaurora.org>.
Change-Id: I81e8e72e7fa219f12dfe8ec39836eb8eb3c4c7b0
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
Falkor is susceptible to branch predictor aliasing and can
theoretically be attacked by malicious code. This patch
implements a mitigation for these attacks, preventing any
malicious entries from affecting other victim contexts.
Change-Id: I535d423c2cefaf93627267b867bf0846e502d4c1
Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org>
[will: fix label name when !CONFIG_KVM and remove references to MIDR_FALKOR]
Signed-off-by: Will Deacon <will.deacon@arm.com>
Git-commit: ec82b567a74fbdffdf418d4bb381d55f6a9096af
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[sramana@codeaurora.org: Use only the link stack sanitization routines,
and leave Falkor related BP hardening code]
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
Set the appropriate regulator voltage to run csiphy in
cphy mode.
Change-Id: I1d6d65115e294dbf72560c8066b45bed0b03b92a
Signed-off-by: Vijay kumar Tumati <vtumati@codeaurora.org>
MAC addresses provisioning thru CNSS is usually done by OEM drivers.
Debugfs interfaces can be used for internal testing.
Change-Id: I1a2693835ac09619baf03ee7d2e1b69dbe48559f
Signed-off-by: Sameer Thalappil <sameert@codeaurora.org>
Add midr value for kryo2xx big cores to apply errata workarounds for
branch prediction hardening.
Change-Id: I7ca9cfa3e6b48d5af78a5297cb76ebe6f52e519e
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
Cortex-A57, A72, A73 and A75 are susceptible to branch predictor aliasing
and can theoretically be attacked by malicious code.
This patch implements a PSCI-based mitigation for these CPUs when available.
The call into firmware will invalidate the branch predictor state, preventing
any malicious entries from affecting other victim contexts.
Change-Id: I554536e8e5cb3839e102299da8f5b944415b1880
Co-developed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Git-commit: aa6acde65e03186b5add8151e1ffe36c3c62639b
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
As we're about to introduce a new workaround that is specific to
Cortex-A73, let's define the coresponding MIDR.
Change-Id: Iabb0e83a0eadddbde458fdafd1224e442b6f3e63
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Git-commit: 199fd2bff4040985fbd7853cc39b7245fcf54bb9
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[sramana@codeaurora.org: Resolve trivial merge conflicts]
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
Hook up MIDR values for the Cortex-A72 and Cortex-A75 CPUs, since they
will soon need MIDR matches for hardening the branch predictor.
Change-Id: I59af5ea4af17198aa70d2ba4b25f729a562727ee
Signed-off-by: Will Deacon <will.deacon@arm.com>
Git-commit: a65d219fe5dc7887fd5ca04c2ac3e9a34feb8dfc
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[sramana@codeaurora.org: Resolve trivial merge conflicts]
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
Some minor erratum may not be fixed in further revisions of a core,
leading to a situation where the workaround needs to be updated each
time an updated core is released.
Introduce a MIDR_ALL_VERSIONS match helper that will work for all
versions of that MIDR, once and for all.
Change-Id: Icbb685f79205ba45f9c990d83cf961616b0d96b7
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Git-commit: 06f1494f837da8997d670a1ba87add7963b08922
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[sramana@codeaurora.org: Fix merge conflicts]
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
Aliasing attacks against CPU branch predictors can allow the attacks to
redirect speculative control flow on some CPUs and potentially divulge
information from one context to another.
This patch adds initial skeleton code behind a new Kconfig option to
enable implementation-specific mitigations against these attacks for
CPUs that are affected.
Change-Id: I07fba1943dd63df8951bf68fac947666100e5559
Co-developed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Git-commit: 0f15adbb2861ce6f75ccfc5a92b19eae0ef327d0
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[sramana@codeaurora.org: Fix merge conflicts and make it
compilable on msm-4.4]
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
Adding support to decode 12 bit raw metadata
at CSID.
Change-Id: I89bb9f69f3f004df29b1498761e9a54fb88cdef0
Signed-off-by: Vijay kumar Tumati <vtumati@codeaurora.org>
The i2c-msm-v2 driver trying to get the clocks too early, but
the clock framework is not initialized yet. The change of the
initcall type reducing deferred calls and improving boot time.
Info:
[0.212999] i2c-msm-v2 78b6000.i2c: probing driver i2c-msm-v2
[0.213172] i2c-msm-v2 78b6000.i2c: error on clk_get(core_clk):-517
-- snipped --
[0.275922] i2c-msm-v2 78b6000.i2c: probing driver i2c-msm-v2
[0.276086] i2c-msm-v2 78b6000.i2c: error on clk_get(core_clk):-517
-- snipped --
[0.302980] msm_mpm_dev_probe(): Cannot get clk resource for XO: -517
[0.303394] i2c-msm-v2 78b6000.i2c: probing driver i2c-msm-v2
-- snipped --
Change-Id: Ia8c110b5f67eeec07586adb30ec3a7aff7ce265a
Signed-off-by: Atanas Filipov <afilipov@codeaurora.org>
Upgrade machine driver to support 32 channels include expose mixer
controls for TERT/QUAT slot_number and slot_width and also slot
mapping configuration.
Change-Id: Ie0a73cf45a6daf3d4aced02cd99aa0ec09cb7c48
Signed-off-by: Cong Tang <congt@codeaurora.org>
MAC address programmed thru CNSS could be provisioned or
derived MAC address. So add support for programming the derived
MAC address.
Change-Id: I2fae232e32a8600949c286346acd05afefd94ef8
Signed-off-by: Sameer Thalappil <sameert@codeaurora.org>
Update audio header files include new macro and structure definitions
for 32 channels support.
Change-Id: Idf5e92f7fda4b820b1a7f01001a683772281d8ba
Signed-off-by: Cong Tang <congt@codeaurora.org>
Disable the SPI based CAN controller on msm8996 CV2X boards
since they are using the USB based CAN controller now.
Change-Id: I57cccee0b9ffa59f516747350160907960048a6a
Signed-off-by: Gustavo Solaira <gustavos@codeaurora.org>
