Provide means to set ship mode on smb138x charger. While in parallel
charger mode make the main charger set ship mode on smb138x before
calling ship mode on itself.
Change-Id: I9b96b425829520d95632aa32d2297940cca5e254
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
For modem SSR, APPS needs to halt modem consumer channels after
shutdown to make sure GSI FW does not access any modem's memory.
Change-Id: I6889a2ad509e0b1104ef8c3f65f24fe39b10745d
CRs-Fixed: 2008582
Acked-by: Ady Abrahan <adya@qti.qualcomm.com>
Signed-off-by: Skylar Chang <chiaweic@codeaurora.org>
Expose a new API from GSI driver to allow client driver to
disable channel for other Execution Environment.
This API will be used as part of SSR cleanup.
Change-Id: I3b9400643aff76ca2195a597aba9ea18aab3085e
CRs-Fixed: 2008582
Acked-by: Ady Abrahan <adya@qti.qualcomm.com>
Signed-off-by: Skylar Chang <chiaweic@codeaurora.org>
Enable watchdog node for sdm630 which is used to detect system hang.
Change-Id: Idfb307dd991e17e0030921e03c6f8a04afb9bc1d
Signed-off-by: Saranya Chidura <schidura@codeaurora.org>
Added CONFIG_CORESIGHT_CTI and CONFIG_CORESIGHT_CTI_SAVE_DISABLE
in perf_defconfig of SDM660 to enable cti without save-restore
functionality for CPU cores.
Change-Id: I19a2fb8a3097bac910bb5e50c9a80d84f03098d3
Signed-off-by: Saranya Chidura <schidura@codeaurora.org>
Added CONFIG_CORESIGHT_CTI_SAVE_DISABLE in kconfig of
coresight to choose CTI without save-restore functionality
for CPU cores.
Change-Id: I48128fbeda293a73d78946b8c222b5d0393c7595
Signed-off-by: Saranya Chidura <schidura@codeaurora.org>
To avoid running into issues with the MMNOC RCG being enabled due
to an enable request from a secure world entity whilst the HLOS code
has disabled its parents, park the RCG at CXO when its disabled.
Change-Id: I98e2efaed01ee4e92a457c56f2e276985882dbbb
Signed-off-by: Taniya Das <tdas@codeaurora.org>
If the RCG frequency table does not have CXO as one of its supported
frequencies, and if a client calls clk_enable on it prior to setting
its rate, the current RCG code would configure it to the lowest
supported frequency instead which would then lead the subsequent
call to update the configuration to fail because the parent PLLs are
not active. Correct this behavior. Also update the index in case cxo_f
frequency table is used for rcg configure.
Change-Id: Ib2c09f9f503724bafd32b963b5b0ea84da7c4b7b
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Not all MHI hardware channels support burst mode, add
support to enable burst mode per channel basis.
CRs-Fixed: 1027069
Change-Id: Icd3061f1a1a4b4b3dab8f9fe3b989a8afefd18b2
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
Add support for new MHI hardware channel 102 to be
use by MHI clients as ADPL channel.
CRs-Fixed: 1027069
Change-Id: Ib3c2019fc269064d097bb7f40f01d4580e63a603
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
MHI transaction status stores the OVERFLOW status
received from device. MHI clients uses this
status to determine overflow buffers, do
not clear the status.
CRs-Fixed: 1042516
Change-Id: Iaaff06c1c39775d6a33ca17851f1e1579b2a2ecb
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
Currently the notifier does not respond to main psy changed events, so
changes in ICL will not schedule the status change work. Furthermore,
the status change work does not re-run the FCC splitting which is
dependent on the settled ICL.
First, add the main psy as one of the triggers for the status changed
work. Second, re-run the FCC and FV voteable elections to re-split the
FCC based on the new ICL.
Change-Id: I1f5f2e176ec470c9c71ff4a0787ffa0cc5828ebc
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
Initialize remote_host value for smem corner case where
variable can be used without being set.
CRs-Fixed: 2004073
Change-Id: Iec3b0d66e7f557efa7167bdc2c1be9b02dcd4e96
Signed-off-by: Chris Lew <clew@codeaurora.org>
The maximum PM8998 S13 voltage is 1.136 V. Update the
regulator-max-microvolt property for the PM8998 S13
device to reflect this.
CRs-Fixed: 2010419
Change-Id: Ic9cbd802fed8b0b48c872341efb429f0616b423a
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Initialize values for variables that may be used with out
the value being set in glink corner cases.
CRs-Fixed: 2004073
Change-Id: If0e813bf1601dd6c1288bc22864ddd2fb3dbf90f
Signed-off-by: Chris Lew <clew@codeaurora.org>
When checking for available spaces, check available spaces on
both bounce buffer ring and transfer ring and return min.
Change-Id: I9208b46c32821de3f5d9e3d828087d7bc29b9546
CRs-Fixed: 1055681
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
Add missing state MHI_STATE_RESERVE to MHI states
look up table.
CRs-Fixed: 1049595
Change-Id: I9a6bd2750f81f6cabc1e7b5aff488b4a01f7897d
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
Currently, return value for SMCINVOKE_IOCTL_INVOKE_REQ IOCLT is mixed
with error generated by client. This does not seem right because client
does not understand kernel error code and vice versa.
Change-Id: I77278700c4927facf7aba92a11bfde29b1e8eb38
Signed-off-by: Dinesh K Garg <dineshg@codeaurora.org>
Get the iova for a buffer object from the context
specific address space instead of always defaulting
to the global address space.
Change-Id: Id38c2ca2d6bad334beab53d8bcf8eb5cf5b1bb99
Signed-off-by: Sushmita Susheelendra <ssusheel@codeaurora.org>
Return the current status of the fence (0 for retired, -EBUSY for
active) if an absolute timeout of 0 is passed to MSM_IOCTL_WAIT_FENCE.
This allows the user space to check the status of the fence without
an awkward timeout or an inadvertent kernel message.
Change-Id: Ic0dedbad66adfabed24aeb6692abb2765ee37f24
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
The PFP/ME and GPMU memory needs to be GPU accessible but it
does not need to be written by the GPU. Mark them as read-only
to avoid corruption.
Change-Id: Ic0dedbadc848f0a6693a4e57567077bbab38e9a5
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
There isn't any need to be in secure mode when executing the GPMU
initalization so swap out to eliminate it as a variable when
GPMU init goes broken.
Change-Id: Ic0dedbad07b8cde80e257f71999002e9cbc47c24
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Enable pm_runtime for the GPU to keep power collapse from hitting
us while we expect the GPU to be powered.
Change-Id: Ic0dedbad693f1d01776a87bc7a145a65510ac3fb
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
If we do not enable the iommu clocks at attach time they might
be shut off automatically by other devices power collapsing which
would affect our ability to switch the pagetable dynamically.
There is little power downside to just leaving them on all the time,
or at least as long as the main device is attached (in other words,
all the time).
Change-Id: Ic0dedbad8f6d2ee2a2cb9516e062af2421d91052
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
The overrun check for the size of submitted commands is off by one.
It should allow the offset plus the size to be equal to the
size of the memory object when the command stream is very tightly
constructed.
Change-Id: Ic0dedbadec41fb8be84d7522b4dc923dbd537ce5
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
When a fault happens on the Adreno GPU we want to collect
a considerable amount of information to diagnose the problem
including registers, caches, and GPU memory structures (ringbuffers,
etc).
The snapshot collects all of this information following a GPU fault
and encodes it into a binary file format that can be pulled from
debugfs or extracted from a memory dump.
This may seem a duplication of other debug methods (the ->show
functions for example) and while that is true for small numbers
of registers the snapshot goes much further - it collects hundreds
(thousands) of registers in addition to memory and other structures
that would be impractical to dump as ascii. The binary format allows
for the snapshot to be easily shared and post-processed in different
ways to extract patterns.
Add the basic snapshot infrastructure and enable ringbuffer, register
and shader bank collection for A5XX targets.
Change-Id: Ic0dedbadcf0513096d05870f522ac73da74ceb31
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
There are some use cases wherein we need to turn off hardware clock
gating before reading certain registers. Modify the A5XX HWCG function
to allow user to enable or disable clock gating at will.
Change-Id: Ic0dedbade1264785b3436099e638a5678a62818f
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Update the list of the A5XX register ranges that can be read on a
hang. The new list adds some registers that were previously missed,
and omits registers that are write only.
Change-Id: Ic0dedbadaf6969892c0563d9cfd8fa2869008417
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
