On MSMCOBALT, the ahb_clk_src needs its sources to be enabled for
it to configure to a new frequency. Hence, force enable the PLL
and XO sources everytime it is scaled.
CRs-Fixed: 1060894
Change-Id: Ib2f5277f14b1484838439a9bb756358421737bd4
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Update the video core clock frequency tables on MSMCOBALT v2.
CRs-Fixed: 1071940
Change-Id: I2858da0e32dfa4ea5bc14395e884aabf832fa8f6
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
The load balancer restrictions are in place to control the tasks
migration from the lower capacity cluster to higher capacity
cluster to save power. The assumption here is that higher capacity
cluster will have higher power cost which may not be necessarily
true for all platforms. Use power cost based checks instead of
capacity based checks while applying the inter cluster migration
restrictions.
Change-Id: Id9519eb8f7b183a2e9fca87a23cf95e951aa4005
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
When attempting to restore multiple endpoint's configuration
space over a switch or bridge, only restore for the ones
that are accessible and powered on.
Change-Id: Ie6234ae30ad47a063982e5cc50f4ecedf1f61de2
Signed-off-by: Tony Truong <truong@codeaurora.org>
Fix the bug introduced by commit 82d4ec9778
("usb: Add support for reset controller framework") which
overrides the core clock rate from device tree.
Change-Id: Ic3ef2229fa8552301e09dfb912e79e044a81324f
Signed-off-by: Vamsi Krishna Samavedam <vskrishn@codeaurora.org>
Optimize the initial rotator session opening time by moving the clock
and BW voting to the start of rotator. Also adjusting the clock
calcuation to include overhead and fudge factor. Create debugfs entry
for supporting override the clock and BW calculation
CRs-Fixed: 1071288
Change-Id: Ia6a84f160d0288ced98bf9f1818d9eabfc2e3963
Signed-off-by: Benjamin Chan <bkchan@codeaurora.org>
WLAN firmware can reject QMI message, improve the logs to
indicate the same.
CRs-Fixed: 1071938
Change-Id: I7ab180e06ececf8136903ee04565b8b4a2bf3524
Signed-off-by: Yuanyuan Liu <yuanliu@codeaurora.org>
Convert the driver to dev_pm_ops from SIMPLE_DEV_PM_OPS
in Goodix TS driver to reduce suspend/resume latency.
Change-Id: I45690b239c73f636538b864f0c4a7e539a02eedb
Signed-off-by: Shantanu Jain <shjain@codeaurora.org>
The PBL spare status registers provide more info
about the reason for PBL failure.
Change-Id: I1dddc7df26caa1556e57128603afd32b2613ebde
Signed-off-by: Amir Samuelov <amirs@codeaurora.org>
When no audio use-cases are active, codec digital core
can be put into power collapse to reduce the power consumption
during codec stand-by. Add support to put core into power
collapse and remove out of the collapse when audio use-cases
are triggered.
CRs-Fixed: 1063742
Change-Id: I0314b7319f2ef02d6125b77e68bf47d065521f6a
Signed-off-by: Meng Wang <mwang@codeaurora.org>
Interrupts are useful for testing and debugging. Enable all fuel gauge
interrupts.
Change-Id: Ic6dd2d1e7f829630dc6eae5ff74fae04f7fc7f9b
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
Some SRAM registers are encoded using a floating point representation.
Add a function to decode these registers into signed micro-unit
integers.
The exponent and mantissa are signed integers represented by two's
complement, and the exponent value is offset by -9. This is a half
float representation stored as:
EEEEE MMMMMMMMMMM
Where E are the exponent bits, and M are the mantissa bits.
To decode this representation the following formula is applied:
2^(exponent - 9) * mantissa
Change-Id: Id9f28a0eeb2a904aca41eb46d0215d80287e0b88
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
Rate converter clock needs to enable for adaptive ANC
(Active Noise Cancellation)to work otherwise noise mic
data will not go to Rx path. Add change to enable rate
converter clock.
Change-Id: I8c83f6305dbc0a40b67bf2ffd53d37a0abdcf953
Signed-off-by: Vidyakumar Athota <vathota@codeaurora.org>
Allow scaling the performance cluster clock to 2.3 GHz using
single core frequency boost on MSMCOBALT v2 speed bin 1 parts.
CRs-Fixed: 1070684
Change-Id: I473a1965989ac652c630b69c6086b74d0bdabfa3
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
The current OSM framework does not support mapping multiple OSM
clock frequencies to the same CPR virtual corner. Enable this
support and update the current clock DT entries accordingly.
CRs-Fixed: 1070684
Change-Id: I3422848cabf221f497eb91f9aae5905e34ebdc84
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Change FnR rule creation prints to low in order to avoid IPC
logging flood.
Change-Id: Ie1f0f48ffc1fd67fc8a2074d3d334fb8cd29c99f
CRs-Fixed: 1064336
Acked-by: Ady Abraham <adya@qti.qualcomm.com>
Signed-off-by: Skylar Chang <chiaweic@codeaurora.org>
