To support more accurate benchmarks, add entry and exit logs
for PCIe functions.
Change-Id: I49f27263722adfaa8ae3973f242faa6a589d3358
Signed-off-by: Tony Truong <truong@codeaurora.org>
To support PCIe MSI on 3.14 kernel, the client's host
driver must use the QGIC IRQ number to request/enable
the interrupt while the client's firmware must use
the SPI number to trigger the interrupt. Therefore,
add this logic in PCIe bus driver to support MSI
interrupts on 3.14 kernel.
Change-Id: I165022281c9e795be8c5e2e4a4faa34d4c004a45
Signed-off-by: Tony Truong <truong@codeaurora.org>
After writing to a PCIe PHY debug register, the wrong
PCIe PHY status register is being read back. This change
corrects the PCIe PHY status register that is read back.
Change-Id: If360aa6f9b4530e4c07acfcc1af684c6d7ecc234
Signed-off-by: Tony Truong <truong@codeaurora.org>
Add PCIe support for thulium. Added enumeration,
interrupts, and hardware configurations support for
PCIe.
Change-Id: I48b2fc8a51303a6aea7b1b2a97c4de25f19ded4c
Signed-off-by: Tony Truong <truong@codeaurora.org>
When searching for the endpoint's capabilities register,
check that the value from the register read is valid.
Change-Id: Ia64de3c75618ca0a51aa4588ac97f2fcb26d8829
Signed-off-by: Tony Truong <truong@codeaurora.org>
When reading shadow registers, the wrong value is being
recovered for root complex L1 register. Currently,
the value being recovered is a shadow of the endpoint's
L1 register. This change will recover the correct shadow
value for RC L1 register.
Change-Id: I82b1810ef8761de90b350743cdd9b24a74efb62f
Signed-off-by: Tony Truong <truong@codeaurora.org>
There is an extra identical call made to check if aux clk
is supported base from PCIe device tree node. There is no
need to do this check twice; therefore, remove the duplicate
call.
Change-Id: If705e98e637287969d68ea2241e62447aa505eb0
Signed-off-by: Tony Truong <truong@codeaurora.org>
Not all the testcases for debugfs needs the calculated offset
of an endpoint's capability register. Therefore, only calculate
the offset of an endpoint's capanility register if that testcase
needs it.
Change-Id: Iffddcea682d8c9344f51a04b57f60ba906b01dc6
Signed-off-by: Tony Truong <truong@codeaurora.org>
When the clients want to enable common clock for the
endpoint, also enable it for the root complex.
Change-Id: I55d5a69be0746a745b073051452d45a38d0a4e65
Signed-off-by: Tony Truong <truong@codeaurora.org>
FSM9010 requires a different PHY sequence. Therefore,
this change adds the PCIe PHY support for FSM9010.
Change-Id: Ic98860d3ac1f7b644b76064032f399f070fc9b47
Signed-off-by: Tony Truong <truong@codeaurora.org>
Add support to enable the clock power management for the
endpoint.
Change-Id: I02bebfeb5d32eb8e1f75ee5feb4c4fff956ece66
Signed-off-by: Tony Truong <truong@codeaurora.org>
Add support to enable the common clock configuration for the
endpoint.
Change-Id: I9f6c33eb6cfa032837a07e437f349a7c1a60704c
Signed-off-by: Tony Truong <truong@codeaurora.org>
The start address of the capability register varies
depending on the endpoint. This change calculates the
endpoint's capability register offset instead of using
a fixed one.
Change-Id: I28a97d316aee8c34afe313838b91fcc06af0847f
Signed-off-by: Tony Truong <truong@codeaurora.org>
In the case of multiple endpoints connected to a bridge,
PM logic is not present. Therefore, this change adds
PM support for when there are multiple endpoints on a bridge.
Change-Id: I5a1876db85d0d161ae537a09a508a93b5099aa56
Signed-off-by: Tony Truong <truong@codeaurora.org>
This PCIe bus driver snapshot is taken as of msm-3.10 commit:
803998b (Merge "ASoC: wcd: don't set autozeroing for conga")
This change adds the PCIe bus driver and its dependecies from
msm-3.10 to msm-3.14. All the files are as is from msm-3.10.
No additional changes were made.
Change-Id: Ia1a2d0eea0cc87c16357c95bfcc4df72e910cd34
Signed-off-by: Tony Truong <truong@codeaurora.org>
