We recently sorted the nodes in dove, orion5x, kirkwood, and armada
370/xp. However, I missed this file. -6281 is fine.
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Add nodes for the two SATA PHYs on kirkwood.
Add node for the one SATA PHY on Dove.
Add pHandles to the PHYs in the sata nodes.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Make it easier to notice the common file for ChromeOS devices based on
the Exynos5250 by giving it the exynos5250 prefix that the boards have.
Signed-off-by: Mark Brown <broonie@linaro.org>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Ensure that unused I2C controllers are not activated, causing problems due
to inappropriate pinmuxing or similar, by marking the controllers as
disabled by default and requiring boards to explicitly enable those that
are in use.
Signed-off-by: Mark Brown <broonie@linaro.org>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Rather than requiring each board to explicitly disable the SPI controllers
it is not using instead require boards to enable those that they are using.
This is less work overall since normally at most one of the controllers is
in use and avoids issues caused by inappropriate pinmuxing.
Signed-off-by: Mark Brown <broonie@linaro.org>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
There is a 16.934MHz fixed rate clock connected to MCLK1 on the CODEC, add
this to the device tree bindings.
Signed-off-by: Mark Brown <broonie@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Exynos5420 SoC has per core thermal management unit.
5 TMU channels 4 for CPUs and 5th for GPU.
This patch adds the device tree nodes to the DT device list.
Nodes carry the misplaced second base address and the second
clock to access the misplaced base address.
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Commit e908d5c5 ("ARM: dts: change status property of dwmmc nodes
for exynos5250") missed out handling the exynos5250 snow dts file.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
For consistency with other device tree nodes, this patch adds missing
spaces after node labels.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
There is no need to use two cells for interrupt specifiers inside the
MCT interrupt map, so this patch simplifies the map to use one cell.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
For MCT block compatible with "samsung,exynos4412-mct", that uses PPI
interrupts for local timers, only one local interrupt needs to be
specified, since it is a per-processor interrupt.
This allows moving MCT node of Exynos4x12 SoCs back to common
exynos4x12.dtsi, since they have the same set of interrupts to be
specified, which was the only difference.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
MCT is not an interrupt controller and so there is no point for device
tree nodes representing it to contain interrupt-controller
and #interrupt-cells properties.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add the device-tree binding for the PWM controller to Exynos5250 and Exynos5420
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Olof Johansson <olofj@chromium.org>
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add SPI device tree nodes to Exynos5420 SoC
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds dma controller node info on Exynos5420.
Exynos5420 has adma for audio IPs. As adma clk is dependent
on audss clk provider that will be added later.
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch removes device tree node of SDHCI0 controller and replaces
it with MSHC to enable support MMC 4.4 and improve performance of eMMC
memory.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
All SoCs from Exynos4x12 series contain the MSHC block, so its node can
be located in exynos4x12.dtsi. In addition, missing clock specifiers
are added, generic SoC attributes are moved from board dts files
to common dtsi file of SoC family and the node is renamed to a more
generic name to follow node naming recommendations.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Clock lookup information is required as driver can manipulate
clock rate properly.
Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The device tree sent upstream for exynos5250-snow encoded the search
key as CAPSLK. However in all ChromeOS kernels it is L_META. One can
certainly have long debates about which it ought to be, but I'm
proposing setting it to L_META because:
* That's how _all_ ChromeOS kernels do it and will do it.
* There is no L_META key on the board, so it's nice to have.
* For those people who really want it to be caps lock, they can use
xmodmap or somesuch.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
When the exynos5250 device tree was sent upstream the keyboard mapping
was missing the 2nd instance of the "\" key. There are two copies of
the "\" because it simply has a different row and column on US and
non-US keyboards.
For more details, see the previous patch in this series: (mkbp: Fix
problems with backslash).
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* Global
- Use interrupt macros
- Use #include in device tree sources
- Tidyup DT node naming
* emev2 (Emma Mobile EV2) SoC
- Setup internal peripheral interrupts as level high
- Use interrupt macros in DT files
- Add clock tree description in DT
* r8a7791 (R-Car M2) SoC
- Correct GPIO resources
* r8a7791 (R-Car M2) based Koelsch board
- Configure PFC and GPO
- Use r8a7791 suffix for IRQC compat string
- Add DT reference
* r8a7790 (R-Car H2) based Lager board
- Include all 4 GiB of memory
- Use r8a7790 suffix for IRQC and MMCIF compat strings
- Enable MMCIF
- Add default PFC settings
* r8a7778 (R-Car M1) SoC
- Suffix for INTC compat string
- Add HSPI, MMCIF, SDHI and I2C suppport on DTSI
- Correct pin control device addresses
* r8a7778 (R-Car M1) based Bock-W board
- Use falling edge IRQ for LAN9221 in DT reference
- Enable I2C, HSPI0, MMCIF and SDHI
- Correct MMC pin conflict
- Remove manual PFC settings from DT reference
- Add default PFC settings
* r8a7779 (R-Car H1) SoC
- Add HSPI and SDHI support
- Suffix for INTC compat string
* r8a7779 (R-Car H1) based Marzen board
- Enable HSPI0 and SDHI in DTS
- Remove SDHI0 WP pin setting
- Use falling edge IRQ for LAN9221 in DT reference
- Add SDHI support
* r8a7740 (R-Mobile A1) SoC
- Suffix for INTC compat string
- Add FSI support via DTSI
- Use interrupt macros
* r8a7740 based Armadillo board
- Add FSI support for DTS
- Use low level IRQ for ST1231 in DT reference
* r8a73a4 (SH-Mobile APE6) SoC
- Use interrupt macros in DT files
* r8a73a4 (R-Mobile APE6) based ape6evm board
- Include all 2 GiB of memory
* r8a73a0 (SH-Mobile AG5) SoC
- Correct SDHI compat string
* r8a73a0 (SH-Mobile AG5) based kzm9d board
- Add GPIO keys and Add PCF8575 GPIO extender to DT
- Enable DSW2 with gpio-keys
- Use falling edge IRQ for LAN9221 in DT reference
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Merge tag 'renesas-dt-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
From Simon Horman:
Renesas ARM based SoC DT updates for v3.14
* Global
- Use interrupt macros
- Use #include in device tree sources
- Tidyup DT node naming
* emev2 (Emma Mobile EV2) SoC
- Setup internal peripheral interrupts as level high
- Use interrupt macros in DT files
- Add clock tree description in DT
* r8a7791 (R-Car M2) SoC
- Correct GPIO resources
* r8a7791 (R-Car M2) based Koelsch board
- Configure PFC and GPO
- Use r8a7791 suffix for IRQC compat string
- Add DT reference
* r8a7790 (R-Car H2) based Lager board
- Include all 4 GiB of memory
- Use r8a7790 suffix for IRQC and MMCIF compat strings
- Enable MMCIF
- Add default PFC settings
* r8a7778 (R-Car M1) SoC
- Suffix for INTC compat string
- Add HSPI, MMCIF, SDHI and I2C suppport on DTSI
- Correct pin control device addresses
* r8a7778 (R-Car M1) based Bock-W board
- Use falling edge IRQ for LAN9221 in DT reference
- Enable I2C, HSPI0, MMCIF and SDHI
- Correct MMC pin conflict
- Remove manual PFC settings from DT reference
- Add default PFC settings
* r8a7779 (R-Car H1) SoC
- Add HSPI and SDHI support
- Suffix for INTC compat string
* r8a7779 (R-Car H1) based Marzen board
- Enable HSPI0 and SDHI in DTS
- Remove SDHI0 WP pin setting
- Use falling edge IRQ for LAN9221 in DT reference
- Add SDHI support
* r8a7740 (R-Mobile A1) SoC
- Suffix for INTC compat string
- Add FSI support via DTSI
- Use interrupt macros
* r8a7740 based Armadillo board
- Add FSI support for DTS
- Use low level IRQ for ST1231 in DT reference
* r8a73a4 (SH-Mobile APE6) SoC
- Use interrupt macros in DT files
* r8a73a4 (R-Mobile APE6) based ape6evm board
- Include all 2 GiB of memory
* r8a73a0 (SH-Mobile AG5) SoC
- Correct SDHI compat string
* r8a73a0 (SH-Mobile AG5) based kzm9d board
- Add GPIO keys and Add PCF8575 GPIO extender to DT
- Enable DSW2 with gpio-keys
- Use falling edge IRQ for LAN9221 in DT reference
* tag 'renesas-dt-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (102 commits)
ARM: shmobile: marzen: enable HSPI0 in DTS
ARM: shmobile: r8a7779: add HSPI support to DTSI
ARM: shmobile: Use r8a7779 suffix for INTC compat string
ARM: shmobile: Use r8a7778 suffix for INTC compat string
ARM: shmobile: Use r8a7740 suffix for INTC compat string
ARM: shmobile: Use sh73a0 suffix for INTC compat string
ARM: shmobile: armadillo: add FSI support for DTS
ARM: shmobile: r8a7740: add FSI support via DTSI
ARM: shmobile: emev2: Setup internal peripheral interrupts as level high
ARM: shmobile: emev2: Use interrupt macros in DT files
ARM: shmobile: Use interrupt macros in r8a73a4 and r8a7778 DT files
ARM: shmobile: Fix r8a7791 GPIO resources in DTS
ARM: shmobile: Include all 4 GiB of memory on Lager DT Ref
ARM: shmobile: Include all 4 GiB of memory on Lager
ARM: shmobile: Include all 2 GiB of memory on APE6EVM
ARM: shmobile: Include all 2 GiB of memory on APE6EVM DT Ref
ARM: shmobile: kzm9g-reference: Add GPIO keys to DT
ARM: shmobile: kzm9g-reference: Add PCF8575 GPIO extender to DT
ARM: shmobile: Koelsch DT reference GPIO LED support
ARM: shmobile: Enable DSW2 with gpio-keys on KZM9D
...
Signed-off-by: Kevin Hilman <khilman@linaro.org>
* r8a7790 (R-Car H1) SoC
- Correct GPIO resources in DT.
This problem has been present since GPIOs were added to the r8a7790 SoC
by f98e10c88a ("ARM: shmobile: r8a7790: Add GPIO controller
devices to device tree") in v3.12-rc1.
* irqchip renesas-intc-irqpin
- Correct register bitfield shift calculation
This bug has been present since the renesas-intc-irqpin driver was
introduced by 443580486e ("irqchip: Renesas INTC External IRQ pin
driver") in v3.10-rc1
* Lager board
- Do not build the phy fixup unless CONFIG_PHYLIB is enabled
This problem was introduced by 48c8b96f21
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Merge tag 'renesas-fixes-for-v3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into fixes
From Simon Horman:
Renesas ARM based SoC fixes for v3.13
* r8a7790 (R-Car H1) SoC
- Correct GPIO resources in DT.
This problem has been present since GPIOs were added to the r8a7790 SoC
by f98e10c88a ("ARM: shmobile: r8a7790: Add GPIO controller
devices to device tree") in v3.12-rc1.
* irqchip renesas-intc-irqpin
- Correct register bitfield shift calculation
This bug has been present since the renesas-intc-irqpin driver was
introduced by 443580486e ("irqchip: Renesas INTC External IRQ pin
driver") in v3.10-rc1
* Lager board
- Do not build the phy fixup unless CONFIG_PHYLIB is enabled
This problem was introduced by 48c8b96f21
* tag 'renesas-fixes-for-v3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: r8a7790: Fix GPIO resources in DTS
irqchip: renesas-intc-irqpin: Fix register bitfield shift calculation
ARM: shmobile: lager: phy fixup needs CONFIG_PHYLIB
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Contrary to the rest of the keyboard, which is connected to the ChromeOS
embedded controller, the power key is hooked up to a GPIO. Add a device
tree node to handle it.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The keyboard on Venice2 is attached to the ChromeOS embedded controller.
Add the corresponding device tree nodes and use the MATRIX_KEY define to
encode keycodes.
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
From Uwe Kleine-König:
* efm32/soc: (1003 commits)
ARM: device trees for Energy Micro's EFM32 Cortex-M3 SoCs
ARM: new platform for Energy Micro's EFM32 Cortex-M3 SoCs
+Linux 3.13-rc4
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Enable USB2 on Beaver, exposed via the mini-PCIe connector.
Signed-off-by: Eric Brower <ebrower@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Modify Tegra30 default USB2 phy_type to UTMI; this matches
power-on-reset defaults and is expected to be the common case.
The current implementation is likely an incorrect
carry-over from Tegra20, where USB2 does default to ULPI.
Signed-off-by: Eric Brower <ebrower@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
We want to follow the name style of DTS that is SoC-board.dts.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Now that support for Intersil ISL12057 RTC chip is available
upstream, let's enable it in NETGEAR ReadyNAS 2120 .dts file
so that the device stop believing it's the 70's.
Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Now that support for Intersil ISL12057 RTC chip is available
upstream, let's enable it in NETGEAR ReadyNAS 104 .dts file
so that the device stop believing it's the 70's.
Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Now that support for Intersil ISL12057 RTC chip is available
upstream, let's enable it in NETGEAR ReadyNAS 102 .dts file
so that the device stop believing it's the 70's.
Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Add HDMI node to the Dalmore device tree and hook up the VDD and PLL
regulators as well as the I2C adapter used for DDC and the GPIO used
for hotplug detection.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Dalmore has a 10.1" WUXGA panel connected to one of the DSI outputs of
the Tegra114.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add the gr3d device tree node. The gr3d block on Tegra114 is backwards-
compatible with the one on Tegra20.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add the device tree for the gr2d hardware found on Tegra114 SoCs.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add device tree nodes for the DSI controllers found on Tegra114 SoCs.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add host1x, DC (display controller) and HDMI devices to Tegra114
device tree.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add a device node for the MIPI calibration block on Tegra114. There is
no need to disable it by default because it only enables the clock while
performing calibration and therefore shouldn't be consuming any power
when unused.
Signed-off-by: Thierry Reding <treding@nvidia.com>
[swarren, add unit address to new DT node name]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The d6 and d7 is connected to PWM, we can use PWM to control it,
so switch to PWM leds.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Add backlight and panel nodes for the Harmony TFT LCD panel.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
