Reduce halt ack timeout to 25 ms from 100 ms to reduce delay in
mss shutdown path.
Change-Id: I935e35d5d848e564aad5987b1652546046f0927d
Signed-off-by: Avaneesh Kumar Dwivedi <akdwived@codeaurora.org>
Add a new RCG clock ops specific for the DP pixel clock source.
Change-Id: I2ec5ddcfd47af8362f76d76d153e30d4e2f45370
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Vote on the CX rail only if the gfx_ldo regulator
is enabled.
CRs-Fixed: 1078568
Change-Id: Ice3a527b9952c0fdee813d8ad152d4c1deea7ecd
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
A few gfx_ldo memory read/write calls use an invalid ldo
base address leading to other corruptions in the system.
Fix this by using the correct LDO base address.
CRs-Fixed: 1078353
Change-Id: I034d473e86b3fe7164d1c9ddad326c9dd77a188f
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
Enable the configuration which keeps the CPR sensors active
when LDO is in auto-bypass mode. The sensors only stay
bypassed when LDO is regulating.
CRs-Fixed: 1027469
Change-Id: I6b8c2a3fd8fe22a64b6d24c458a7c60641195e45
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
Add a DT property to adjust the open-loop voltage for the LDO
corners, this will be useful for voltage adjustments after
LDO characterization.
While at it, update the LDO MIN_VOLTAGE value for 8953.
CRs-Fixed: 1010052
Change-Id: I7479ebbf0ac7253eb355246d36f15a91ce96cd9a
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
Change the LDO_EN bit definition for GFX LDO on MSM8953 and
remove the LDO bypass fusing logic as it is not supported.
While at it, add the debugfs node to disable ldo_mode.
Disable LDO mode: echo 1 > /d/msm_gfx_ldo/ldo_mode_disable
Enable LDO mode: echo 0 > /d/msm_gfx_ldo/ldo_mode_disable
CRs-Fixed: 989270
Change-Id: Ibc7aa921380e89da4963571408b89bc417dec245
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
Remove all reference to internal code name msmtitanium
and replace them with msm8953, as there is an official
announcement for msm8953 SoC.
Change-Id: If99bbf20756a524c5a3bd7ba49366c29e158289e
Signed-off-by: Tirupathi Reddy <tirupath@codeaurora.org>
Enable the PWMs mapped to the RGB module and specify
the lpg-lut-size.
While at it, enable the haptics and flash node.
Change-Id: I83cf7882d1abb96c343973894c2a7ab3f932dfb1
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
Currently one gic interrupt is mapped to one mpm pin.
Support multiple mpm pins to get enabled with single irq
with client drivers using enable_irq_wake API.
Change-Id: Iea575079c24ed0986b74fb6e86c7b8100474f19e
Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
Compilation issues were observed on 32-bit as header files
were not present. Add support to resolve the issue.
Change-Id: I8071405a888cd2b23a068ca5b9c3a7808d13821a
CRs-fixed: 1089405
Signed-off-by: Amey Telawane <ameyt@codeaurora.org>
During the GDSC enable sequence, the GDS_HW_CTRL forces some
clocks to be on to trigger the handshake to unhalt the SMMU
and NOC. Once the handshake completes, the controller asserts
the PWR_ON status and disables the clocks.
If the clock driver tries enabling the SMMU ahb/axi clocks
immediately, there is a possibility that these clocks might
still not have gone through their disable sequence; especially
if the AXI/AHB rates are very low. If this happens, the clock
driver falsely assumes that the clocks are on and returns. Any
SMMU accesses/traffic at this point might lead to a failure since
the clock could turn off.
Change-Id: I544ca82e20e1c026d0ff1881c96edd33bf362b7d
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Sensor temperature read function traverses the
sensor list every time without using any lock. If the
list is undergoing mutation when it is traversed, it may
result in memory violation. For example, the new element
could have added to the list before updating the
next pointer due to out of order execution. This could result
in either NULL pointer dereference or unassigned memory access
violation. Using a lock every time when temperature
is read may mutually exclude it from list mutation, but it impacts
the performance. Sensor addition is an infrequent operation
when compared to sensor temperature read. So adding a lock
to protect against this infrequent operation will add overhead
and deter performance. Use of list_for_each_entry_safe() function
for traversing, won't help. Because this function can help
only if the traversal loop removes the current element, that
is pointed by this iteration.
Use RCU when traversing and updating the list to avoid locks.
RCU ensures list traversal safe addition or deletion happens
and doesn't block the frequent read operation. Replace the
list_for_each_entry_safe() function with rcu safe list
traversal function list_for_each_entry_rcu(), wherever it is
applicable.
Change-Id: I4c05fefa6906ecad408dfd4407b60bc051366f8c
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
Fix the following in qpnp-power-on driver:
- Use GENMASK for bit mask
- Remove unused module parameter
- Use nested comments properly wherever applicable
- Fix conditional block formatting and typos
- Use const qualifier for of_device_id table
Change-Id: Ib9dd9be6cafad4c7aec1c88d9828ef1ebbe2a1c3
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
New requests coming after/in parallel to shutdown are being
returned with DID_ERROR, but this causes the request to be
requeued and retried. These requests are getting pulled by
the shutdown context since the PON request is inserted at
the head of the queue and the queue is run for processing.
The queuecommand in ufs driver allows requests in the context
of shutdown as PON has to be sent to the device, but this
retried regular request also ends up getting submitted after
PON which fails and causes issues in err handling.
Fix this by not relying on the context but looking for the
target lun of the request. Allow only requests directed
towards well known device lun (where PON will be sent) and
block all other requests. Also make sure we mark the
shutdown processing first before taking the write lock so
that we can appropriately fail the regular request.
Change-Id: Iaa442e8e92310ea0761c27af8fda57ffcadadb3d
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
The IOVA allocator used by these calls supports IOVA address
zero so properly handle IOVA address zero.
Change-Id: I012452d4cf3534dfb79e6deb15b7ff74f5e3bb40
Signed-off-by: Liam Mark <lmark@codeaurora.org>
The smb138x device has been duplicated across many board level files.
Refactor the smb138x device to a separate dtsi file so it can be
included in any board level files.
Change-Id: I9520595f2a40e197ad2227a8391bed79412b19f8
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
Add the QSMMU device nodes that is used for address translations on
msmtriton.
Change-Id: Iff419eef01ce58fe540e8f3bd7c8a1553a340d28
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
This enables the assertion of CX ipeak mitigation during
MSS restart.
Change-Id: I113037aabafeacba7079d530ca859833f475f649
Signed-off-by: Gaurav Kohli <gkohli@codeaurora.org>
Clear the CX iPeak bit if it was set by MSS before crash.
MSS sets this bit if it was in Turbo state. In a situation
where all the votes were set (including MSS), It would have
resulted in CDSP throttling. But when MSS is in crashed state,
It cannot be cleared by MSS, So PIL needs to do this. It
would allow possible clearance of throttle state.
Change-Id: Ia561436a362dc5b0e1cb22c30ce9f5b8bb027a1f
Signed-off-by: Gaurav Kohli <gkohli@codeaurora.org>
Add support of PMFALCON PMIC and enable PMIC specific
workarounds in charger driver.
Change-Id: Id21fde25b9b741b9cb570ab5348959715e53e6cb
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
Charger and Fuel Gauge peripherals are on slave-id 0. Update
charger and FG device node to reflect the same.
Change-Id: I99d1e47a20fd5c3304249aa4f6c64e5967874312
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
Correct the required regulator node for Modem PIL for MSMFALCON Interposer
and also enable Modem pil.
Change-Id: I106ae84303f6a0b1de13ce564600f7788dd382b3
Signed-off-by: Gaurav Kohli <gkohli@codeaurora.org>
Add aggre2_snoc_axi_clk handle in USB3 node which is required to be
voted from USB driver before enabling USB core clock for msmfalcon.
Change-Id: I190233c1fc483f3d519e09784ed19e6c09ccb2bd
Signed-off-by: Vijayavardhan Vennapusa <vvreddy@codeaurora.org>
