The APB DMA block handles DMA transfers to and from some peripherals
in the Tegra SOC. It reads from sequential addresses on the memory
bus, and writes repeatedly to the same address on the APB bus.
Two transfer modes are supported, oneshot for transferring a known
size to or from a peripheral, and continuous for streaming data.
In continuous mode, a callback occurs when the buffer is half full
to allow the existing data to be handled and a new request queued.x
v2 changes:
dma API no longer uses PTR_ERR
Signed-off-by: Erik Gilling <konkers@android.com>
Signed-off-by: Colin Cross <ccross@android.com>
Implement cpufreq support for the Tegra SOC. DVFS is handled by the
core virtual cpu clock. The frequencies of the two cores are tied
together, the highest frequency requested by either core determines
the actual frequency.
Signed-off-by: Colin Cross <ccross@android.com>
- Add drivers to clock lookup table
- Add new pll_m entries
- Support I2C U16 divider
- Fix rate reporting on 32.768kHz clock
- Call propagate rate only if set_rate succeeds
- Add support for audio_sync clock
- Add 24MHz to PLLA frequency list
- Correct i2s1/2/spdifout mux
- Add suspend support
- Fix enable/disable parent clocks in set_parent
- Add max_rate parameter to all clocks
- DVFS support
- Add virtual cpu clock with dvfs
- Support clk_round_rate
- Fix requesting very high periph frequencies
- Add quirks for PLLU:
PLLU is slightly different from the rest of the PLLs. The
lock enable bit is at bit 22 instead of 18 in the MISC
register, and the post divider field is a single bit with
reversed values from other PLLs.
- Simplify recalculating clock rates
- Fix UART divider flags
- Remove unused clock ops
Signed-off-by: Colin Cross <ccross@android.com>
The Tegra SOC contains fuses to identify the CPU type and
bin, and a unique id. The CPU info is required to determine
the correct voltages for each cpu and core frequency.
Signed-off-by: Colin Cross <ccross@android.com>
- the reset values for some pin groups in the tegra pin mux can result in
functional errors due to conflicting with actively-configured pin groups
muxing from the same controller. this change adds a known safe, non-
conflicting mux for every pin group, which can be used on platforms
where the pin group is not routed to any peripheral
- also add each pin group's I/O voltage rail, to enable platform code to
map from the pin groups used by each interface to the regulators used
for dynamic voltage control
- add routines to individually configure the tristate, pin mux and pull-
ups for a pingroup_config array, so that it is possible to program
individual values at run-time without modifying other values.
this allows driver power-management code to reprogram individual
interfaces into lower power states during idle / suspend, or to
reprogram the pin mux to support multiple physical busses per
internal controller (e.g., sharing a single I2C or SPI controller
across multiple pin groups)
- move chip-specific data like pingroups and drive-pingroups
out of the common code and into chip-specific code
- fix debug output for group with no pullups
- add a TEGRA_MUX_SAFE function. Setting a pingroup to TEGRA_MUX_SAFE
will automatically select a mux setting that is guaranteed not to
conflict with any of the hardware blocks.
Signed-off-by: Gary King <gking@nvidia.com>
mirror IRQ enable and disable operations on the legacy PPI system
interrupt controller, since the legacy controller is responsible
for responding to wakeup interrupts when the CPU is in LP2 idle mode
save the irq controller state on suspend and restore on resume
Signed-off-by: Gary King <gking@nvidia.com>
The "legacy irq controller" duplicates the functionality of the GIC,
but remains powered during the cpu suspend and idle modes that power
down the CPU and the GIC.
Signed-off-by: Colin Cross <ccross@android.com>
Add missing io address map entries from datasheet.
Add the IRAM area to the statically mapped io regions.
Correct the onewire, USB, and statmon addresses
Signed-off-by: Colin Cross <ccross@android.com>
Some boards that were added after the mass io_pgoffst/io_physio
removal, and were not updated in the original patch. Fixup here.
c.f. original io_pgoffst/io_physio removal
commit 6451d7783b
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (278 commits)
arm: remove machine_desc.io_pg_offst and .phys_io
arm: use addruart macro to establish debug mappings
arm: return both physical and virtual addresses from addruart
arm/debug: consolidate addruart macros for CONFIG_DEBUG_ICEDCC
ARM: make struct machine_desc definition coherent with its comment
eukrea_mbimxsd-baseboard: Pass the correct GPIO to gpio_free
cpuimx27: fix compile when ULPI is selected
mach-pcm037_eet: fix compile errors
Fixing ethernet driver compilation error for i.MX31 ADS board
cpuimx51: update board support
mx5: add cpuimx51sd module and its baseboard
iomux-mx51: fix GPIO_1_xx 's IOMUX configuration
imx-esdhc: update devices registration
mx51: add resources for SD/MMC on i.MX51
iomux-mx51: fix SD1 and SD2's iomux configuration
clock-mx51: rename CLOCK1 to CLOCK_CCGR for better readability
clock-mx51: factorize clk_set_parent and clk_get_rate
eukrea_mbimxsd: add support for DVI displays
cpuimx25 & cpuimx35: fix OTG port registration in host mode
i.MX31 and i.MX35 : fix errate TLSbo65953 and ENGcm09472
...
* git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-2.6-irqflags:
Fix IRQ flag handling naming
MIPS: Add missing #inclusions of <linux/irq.h>
smc91x: Add missing #inclusion of <linux/irq.h>
Drop a couple of unnecessary asm/system.h inclusions
SH: Add missing consts to sys_execve() declaration
Blackfin: Rename IRQ flags handling functions
Blackfin: Add missing dep to asm/irqflags.h
Blackfin: Rename DES PC2() symbol to avoid collision
Blackfin: Split the BF532 BFIN_*_FIO_FLAG() functions to their own header
Blackfin: Split PLL code from mach-specific cdef headers
* 'next-spi' of git://git.secretlab.ca/git/linux-2.6: (53 commits)
spi/omap2_mcspi: Verify TX reg is empty after TX only xfer with DMA
spi/omap2_mcspi: disable channel after TX_ONLY transfer in PIO mode
spi/bfin_spi: namespace local structs
spi/bfin_spi: init early
spi/bfin_spi: check per-transfer bits_per_word
spi/bfin_spi: warn when CS is driven by hardware (CPHA=0)
spi/bfin_spi: cs should be always low when a new transfer begins
spi/bfin_spi: fix typo in comment
spi/bfin_spi: reject unsupported SPI modes
spi/bfin_spi: use dma_disable_irq_nosync() in irq handler
spi/bfin_spi: combine duplicate SPI_CTL read/write logic
spi/bfin_spi: reset ctl_reg bits when setup is run again on a device
spi/bfin_spi: push all size checks into the transfer function
spi/bfin_spi: use nosync when disabling the IRQ from the IRQ handler
spi/bfin_spi: sync hardware state before reprogramming everything
spi/bfin_spi: save/restore state when suspending/resuming
spi/bfin_spi: redo GPIO CS handling
Blackfin: SPI: expand SPI bitmasks
spi/bfin_spi: use the SPI namespaced bit names
spi/bfin_spi: drop extra memory we don't need
...
* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (96 commits)
apic, x86: Use BIOS settings for IBS and MCE threshold interrupt LVT offsets
apic, x86: Check if EILVT APIC registers are available (AMD only)
x86: ioapic: Call free_irte only if interrupt remapping enabled
arm: Use ARCH_IRQ_INIT_FLAGS
genirq, ARM: Fix boot on ARM platforms
genirq: Fix CONFIG_GENIRQ_NO_DEPRECATED=y build
x86: Switch sparse_irq allocations to GFP_KERNEL
genirq: Switch sparse_irq allocator to GFP_KERNEL
genirq: Make sparse_lock a mutex
x86: lguest: Use new irq allocator
genirq: Remove the now unused sparse irq leftovers
genirq: Sanitize dynamic irq handling
genirq: Remove arch_init_chip_data()
x86: xen: Sanitise sparse_irq handling
x86: Use sane enumeration
x86: uv: Clean up the direct access to irq_desc
x86: Make io_apic.c local functions static
genirq: Remove irq_2_iommu
x86: Speed up the irq_remapped check in hot pathes
intr_remap: Simplify the code further
...
Fix up trivial conflicts in arch/x86/Kconfig
Commit c074512 (imx-esdhc: update devices registration) renamed
MX35_INT_MMC_SDHC2 to MX35_INT_ESDHC2 which broke expansion of the
MXC_INT_MMC_SDHC2 macro.
As (the only user of MXC_INT_MMC_SDHC2) is only used on
mx31 use the MX31 prefixed symbol to define its resources. Moreover to
reduce further confusion mxcsdhc_device0 is fixed accordingly and the MXC
prefixed symbols are removed.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add required platform definitions for QT602240 touchscreen on I2C2 bus.
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add required platform definitions for si470x radio device on Samsung
Goni board.
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
[kgene.kim@samsung.com: minor title fixes]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add required platform definitions for S6E63M0 LCD controller on Samsung
Goni board.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
[kgene.kim@samsung.com: minor title fixes]
[kgene.kim@samsung.com: fix build error]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds suspend-to-ram support for S5PV210.
Note. This patch is confirmed on SMDKV210 and SMDKC110 board.
Signed-off-by: Jongpill Lee <boyko.lee@samsung.com>
Signed-off-by: Sangbeom Kim <sbkim73@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch fixes build error by S3C2410 PM Suspend debug option
due to undefined address.
Signed-off-by: Sangbeom Kim <sbkim73@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Samsung S5P SoCs have the same interrupt type defines for both
external interrupts and gpio interrupts. This patch removes all
duplicates from S5PC100 and S5PV210 specific includes as well as
gpio interrupt code and put a common defines to plat/irqs.h
NOTE: Do not use this for S5P6440 and S5P6450.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
[kgene.kim@samsung.com: add note for S5P64X0]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds a common callback for gpio_to_irq() for external and
gpio interrupts for Samsung SoCs.
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Cc: Ben Dooks <ben-linux@fluff.org>
[kgene.kim@samsung.com: moved samsung_gpiolib_to_irq() for s3c24xx build]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch moves external interrupt definitions from mach/gpio.h
to mach/regs-gpio.h for consistency with S5PV210.
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
S5PC100 SoC can use common S5P GPIO interrupt code. This patch
removes specific S5PC100 gpio interrupts code and adds required
defines and code to make use of common S5P code.
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
S5PV210/S5PC110 can use common S5P GPIO interrupt code.
This patch adds required defines and code to make use of it.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
[kgene.kim@samsung.com: minor title fixes]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds common code to enable support of GPIO interrupt on
S5P SoCs.
The total number of GPIO pins is quite large on S5P SoCs. Registering
irq support for all of them would be a resource waste. Because of that
the interrupt support for standard GPIO pins is registered dynamically
by the s5p_register_gpio_interrupt() function.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
[kgene.kim@samsung.com: minor title fixes]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add the necessary definitions and mapping information to enable the
s3c-hsotg gadget to build.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add required platform definitions for MMC power regulators on Samsung
Goni board. GPIO pin GONI_EXT_FLASH_EN has been transferred from machine
startup code to fixed voltage regulator.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add required platform definitions for s3c-hsotg driver to enable usb
gadget support on Samsung Goni board.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Since commit 67a38950f0917aecfe1a3e46720d8bbb0020 there is no need
to set pixel clock for the s3c-fb driver's window information.
The correct pixel clock value can be automatically calculated from
the other screen parameters. This patch removes the redundant pixel clock
parameter.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Change the default upper_margin and vsync_len to get rid of repeated last
line on the display.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
All the S5P series SoCs use the 'struct clksrc_clk' type to represent the
armclk. So the clk_arm clock instance available in the plat-s5p clock code
is not used in any of the S5P series SoCs.
This patch removes the unused clk_arm instance from plat-s5p clock code.
Reported-by: Jaecheol Lee <jc.lee@samsung.com>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch removes redundant selection PLAT_S5P in the CPU_S5P64XX config.
Because PLAT_S5P is selected if select ARCH_S5P64XX in the plat-s5p/Kconfig.
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The selection PLAT_S5P is selected with plat-s5p/Kconfig.
So remove it form each CPU_S5PXXXX config.
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
[kgene.kim@samsung.com: edited title]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
In case of S5PV310/S5PC210, it uses the SPARSEMEM as default memory
configuration. So moved to ARCH_S5PV310 config.
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
[kgene.kim@samsung.com: edited title]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
In case of S5PV210/S5PC110, it uses the SPARSEMEM as default memory
configuration. So moved to ARCH_S5PV210 config.
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
[kgene.kim@samsung.com: edited title]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds to support Torbreck board of aESOP community using
Samsung S5PV210 SoC.
Signed-off-by: Kyuho Choi <chlrbgh0@gmail.com>
Signed-off-by: Hyunchul Ko <ghcstop@gmail.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The physical address of SYSCON(System Controller) is wrong.
This patch fixs this wrong physical address value from 0x10020000 to 0x10010000.
Signed-off-by: Boojin Kim <boojin.kim@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
It is reported by Junseok Jung that using clz instruction is
better instead of using for-loop to find the interrupt source.
This patch modifies interrupt source searching code using __ffs().
The __ffs() is implemented using clz instruction.
Suggested-by: Junseok Jung <jundols.jung@samsung.com>
Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds support Watchdog Timer for S5PV310 and S5PC210.
Signed-off-by: Jemings Ko <jemings@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds support RTC for S5PV310 and S5PC210.
Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Jemings Ko <jemings@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds DMC(DRAM Memory Controller) map_desc table.
Because some driver such as CPUFREQ need to access DMC register.
Signed-off-by: Jaecheol Lee <jc.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch is to support keypad device to the GONI board.
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
