The secure buffer registers were not being programmed in the soft
reset path which was causing a failure for the critical packets
workaround and forcing a hard reset.
CRs-Fixed: 1009194
Change-Id: Ic0dedbad998767a1ffdfe265e52fae7baa18d203
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Allow 5XX targets to preempt quickly from an atomic context. In
particular this allows quicker transition from a high priority
ringbuffer to a lower one without having to wait for the worker
to schedule.
CRs-Fixed: 1009124
Change-Id: Ic0dedbad01a31a5da2954b097cb6fa937d45ef5c
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Remove some unused gpudev hooks and further segment the A4XX and
A5XX specific code into their respective areas. Remove some bits
that are only applicable to 4XX from the 5XX side.
CRs-Fixed: 1009124
Change-Id: Ic0dedbadc324b979583d7a3998195bf15ac537f6
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
It is no longer power efficient to independently enable and disable
the MMU clocks. We can safely enable and disable them with the rest
of the GPU clocks and take back the infrastructure needed to handle
the clocks.
CRs-Fixed: 1009124
Change-Id: Ic0dedbadc48095eada9c5fce6004475a2cb0f0a9
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
The memstore shared between the CPU and GPU is old but can not be
messed with. Rather than stealing values from it where available,
add a new block of shared memory that is exclusive to the driver
and GPU. This block can be used more freely than the old
memstore block.
Program the GPU to write the RPTR out to an address the CPU can read rather
than having the CPU read a GPU register directly. There are some very
small but very real conditions where different blocks on the GPU have
outdated values for the RPTR. When scheduling preemption the value read
from the register could not reflect the actual value of the RPTR in the CP.
This can cause the save/restore from preemption to give back incorrect RPTR
values causing much confusion between the GPU and CPU.
Remove the ringbuffers copy of the read pointer shadow.
Now that the GPU will update a shared memory address with the
value of the read pointer, there is no need to poll the register
to get the value and then keep a local copy of it.
CRs-Fixed: 987082
Change-Id: Ic44759d1a5c6e48b2f0f566ea8c153f01cf68279
Signed-off-by: Carter Cooper <ccooper@codeaurora.org>
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Currently adreno_ft_regs_val is getting updated at the time of
first submission or on the expiry of fault_timer.
If the fault_timer expires exactly at the time of inflight becomes 0
and there is an immediate submission for which GPU finishes the work
within short time. Then there is a chance to read the fault registers
in fault_detect_read() and fault_detect_read_compare() with less
time gap and declare it as a fault.
Stop the timer before reading fault registers and start it again.
CRs-Fixed: 1043478
Change-Id: Ib35104adf7b3618f94c6adf7fab531abffea3f76
Signed-off-by: Rajesh Kemisetti <rajeshk@codeaurora.org>
Turn off the camif interrupts when camif is disabled and turn them
on when camif is enabled. Also, improve the code to keep track of
interrupts that are enabled by updating them in the function that
sets interrupts instead of doing it in multiple places.
CRs-Fixed: 1037272
Change-Id: I1cc965696c06bd3901d86668aaf597abb3ef2d6d
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
It is required to use phy-msm-qusb-v2.c driver with msmcobalt platform.
Hence use "qcom,qusb2phy-v2" instead of "qcom,qusb2phy" as compatiable
string with QUSB PHY related device node on msmcobalt.
Change-Id: I8d8ed29215f326801ba4e60794cc63e4eaeeb97e
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
Controller driver passes current speed to QUSB2 PHY driver in
the flags parameter. Determine linestate using speed,
mode and cable connection status. This deprecates the older
mechanism where linestate was determined by reading the now
obsoleted QUSB2PHY_PORT_UTMI_STATUS register.
Change-Id: I682eb250964f32f93d7b31dae0291aca7fa44362
Signed-off-by: Devdutt Patnaik <dpatnaik@codeaurora.org>
DP/DM linestate is needed by the QUSB2 PHY driver to configure the
polarity of DP/DM transition triggers for exiting low power mode.
This was previously available via the QUSB2PHY_PORT_UTMI_STATUS
PHY register which is now deprecated. In order to correctly determine
the interrupt polarity we need to pass the current operating speed
to the QUSB2 PHY driver. The PHY driver uses mode, speed and
cable connection status to determine the linestate and configure
interrupt polarities for wake up. Add logic to determine operating
speed for host and device mode cases.
Change-Id: Iaede1269f514a314bd9717a33100f748e7753b2a
Signed-off-by: Devdutt Patnaik <dpatnaik@codeaurora.org>
Update the device node for QUSB2 PHY with the recommended
register initialization sequence for host mode.
This is needed to fix HS enumeration issues due to port
reset failure.
Change-Id: I8cfed672ff02cd61beb956116f9fcd365211cf11
Signed-off-by: Devdutt Patnaik <dpatnaik@codeaurora.org>
commit 77f6fd8044 ("usb: pd: Add support to notify plug
orientation via extcon") added an additional extcon notifier
to indicate orientation. But for the PE_SNK_STARTUP case
the change inadvertently notifies EXTCON_USB for all sink
states when it should just be for psy_type==USB|USB_CDP.
Add the missing curly braces to the if statement.
Change-Id: I19d424ff0d46cc0134210424a7d431b331cbf963
Signed-off-by: Jack Pham <jackp@codeaurora.org>
Add the ipc-spinlock entry to facilitate locking between apps and
non-apps processors.
CRs-Fixed: 1043377
Change-Id: I097e5464ec6ab80c12bcdb5f38d0599fa40da9ee
Signed-off-by: Dhoat Harpal <hdhoat@codeaurora.org>
compare size of allocated cal data buffer from heap
and count bytes provided to write by user to avoid
heap overflow for write cal data.
Change-Id: Id70c3230f761385489e5e94c613f4519239dfb1f
CRs-Fixed: 1032174
Signed-off-by: Anand Kumar <anandkumar@codeaurora.org>
New codec child nodes are added to handle wsa881x
enable pin. Add all the child devices of codec.
CRs-Fixed: 1041199
Change-Id: I889922a0c36ec80ee6ede95b2f19f80791323332
Signed-off-by: Yeleswarapu Nagaradhesh <nagaradh@codeaurora.org>
Add wcd934x gpio controller as child to codec node
and add all child devices of codec.
CRs-Fixed: 1041199
Change-Id: I32ad5c5c8c9dd30a79818c873cfe1d121fd62d49
Signed-off-by: Yeleswarapu Nagaradhesh <nagaradh@codeaurora.org>
Add gdsc_mdss, gdsc_camss_top, gdsc_venus references in order
to enable client side clocks during QoS configuration. Also
include mmssnoc_axi reference so that we can guarantee bus clock
to be on at the time of QoS configuration in the event
that the initial bandwidth vote from client is 0.
CRs-Fixed: 1043729
Change-Id: If8e08112d065e1327fd54d7b0daf511632aa059f
Signed-off-by: David Dai <daidavid1@codeaurora.org>
This reverts commit 5c7566a29b.
This patch revert some changes in net/netfilter/xt_qtaguid.c as well.
I'll submit another patch to restore those changes.
Change-Id: I2d9251867235a6566b4c676de0546ce046848c91
CRs-Fixed: 1035969
Signed-off-by: Amit Pundir <amit.pundir@linaro.org>
Git-commit: cdb6973ae1
Git-repo: https://android.googlesource.com/kernel/common/
Signed-off-by: Bryse Flowers <bflowers@codeaurora.org>
Module parameter already exists to control enabling service-locator,
which is enabled by default using kernel command line. Hence removing
sysfs entry 'service_locator_status'.
CRs-Fixed: 1025447
Change-Id: Ie302e79ff838837f214ac50ebfaa6e11f0055915
Signed-off-by: Puja Gupta <pujag@codeaurora.org>
Update QUSB2 HS PHY init sequence in host mode to fix
enumeration issues due to port reset operation failure.
Change-Id: I95daf3e3a833f9daeac6190daa33191f9db8cf26
Signed-off-by: Devdutt Patnaik <dpatnaik@codeaurora.org>
In some rare race condition during SSR, modem might
programmed commands to IPA to lock the pipe, and AP will
enable delay on this pipe which will prevent IPA to read
unlock command. In this case IPA HW will be stalled as it
is locked forever on this pipe.
CRs-Fixed: 1040724
Change-Id: Ifc874c9e881eb1b3ccea321679bb272cd427fabb
Acked-by: Ady Abraham <adya@qti.qualcomm.com>
Signed-off-by: Skylar Chang <chiaweic@codeaurora.org>
Currently the type of the parallel power supply is
POWER_SUPPLY_TYPE_BATTERY. Change it to POWER_SUPPLY_TYPE_USB_PARALLEL.
Change-Id: Ic7652e43781f39d3137fb55f2fec2423e457fac4
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
PMCOBALT S5 is an always on regulator that sources the internal
infrastructure for XO. It's minimum operating voltage is 1904 mV.
PMCOBALT S7 has a 900 mV minimum operating voltage.
Update the minimum voltage for PMCOBALT S5 and S7.
Change-Id: I4ec609b45f5313d7c19ff6201742b0c5daf54174
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
