The cleanup_irq() was meant to clear and mask interrupts that were
left enabled in the hardware but there was no interrupt handler
registered for it. Add an error print when it gets invoked.
CRs-Fixed: 1001770
Change-Id: Iccf0daadeb82b0fca29829424439ac225e2b3b88
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
The current code uses handle_level_irq flow handler even if the trigger
type of the interrupt is edge. This can lead to missing of an edge
transition that happens when the interrupt is being handled. The level
flow handler masks the interrupt while it is being handled, so if an edge
transition happens at that time, that edge is lost.
Use an edge flow handler for edge type interrupts which ensures that the
interrupt stays enabled while being handled - at least until it triggers
at which point the flow handler sets the IRQF_PENDING flag and only then
masks the interrupt. That IRQF_PENDING state indicates an edge transition
happened while the interrupt was being handled and the handler is called
again.
CRs-Fixed: 1001770
Change-Id: Id2554c9e6ed79188fa1b64728be464bda45f07ec
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Usage of %p exposes the kernel addresses, an easy target to
kernel write vulnerabilities. With this patch currently
%pK prints only Zeros as address. If you need actual address
echo 0 > /proc/sys/kernel/kptr_restrict
CRs-Fixed: 987011
Change-Id: I6c79f82376936fc646b723872a96a6694fe47cd9
Signed-off-by: Azam Sadiq Pasha Kapatrala Syed <akapatra@codeaurora.org>
Add new UFS clocks to support enabling/disabling the hardware
dynamic gating for their corresponding branch clocks.
CRs-Fixed: 1012355
Change-Id: I4836ad8a775b0ec0375e37d27fcbe380e661a7b2
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Add a new hw_ctl_clk type to allow clock clients to enable
hardware dynamic gating of the clock branch.
Clients should use the clk_enable API on a separate hw_ctl_clk
clock structure to set this bit. Vice-versa for clearing it.
It is mandatory that the clients call clk_enable on the actual
branch clock before enabling the hw_ctl_clk clock.
CRs-Fixed: 1012355
Change-Id: I24e78353fa07f537bafc322dba6b1ffac913cd1d
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Gladiator error driver depends on the ATB clocks to be voted.
Previously, clock voting is done after writing to gladiator
registers.
CRs-Fixed: 1011314
Change-Id: I4d18273c6fc63baf58db1a778a1aaf3cb55e4824
Signed-off-by: Runmin Wang <runminw@codeaurora.org>
Add more detailed log to help debug when the ELF segments relocatable bit
is not set and pil_init_segment bails out.
Change-Id: Id8d941e69b70f1bcf709cedc969aa0500be92039
Signed-off-by: Puja Gupta <pujag@codeaurora.org>
The v0.12 format adds three new fields:
uint32_t chip_family;
uint32_t raw_device_family;
uint32_t raw_device_number;
CRs-Fixed: 1013110
Change-Id: I1699ee96c65809a46331f94938c12fc1dd4d5384
Signed-off-by: Se Wang (Patrick) Oh <sewango@codeaurora.org>
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
Signed-off-by: Runmin Wang <runminw@codeaurora.org>
As per recommendation update the emergency hotplug threshold
for MSMcobalt to 105C from 70C.
CRs-Fixed: 1010111
Change-Id: I69a5583e4e15499c54ce5b2ab0fe0538de303391
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
Configure thermal driver to do low voltage restriction for CX,
APSS and graphics rails, when temperature goes below 5 degree C.
This restriction will be cleared if the tsens temperature goes
above 10 degree C.
CRs-Fixed: 1010111
Change-Id: I36a1ba6adb9ce847ae552d904dff1bbd0ce3cb77
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
Configure the limits hardware with the interrupt to listen for.
limits hardware driver will interact with the trustzone to get
throttling information from the hardware.
CRs-Fixed: 1010120
Change-Id: I56a8396a12e9b96cbed554bb1aed5d6243e6240a
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
With the LMH-DCVSh hardware the frequency mitigation in
the HLOS is not needed. Remove the boot-up frequency mitigation
in KTM for msmcobalt.
CRs-Fixed: 1010111
Change-Id: I105e98968b911f08b67c4e686e74ae6f7555d7be
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
temperature sensor 1 maps to cpu1 and not pop_mem. Remove
the pop_mem alias name defined for temperature sensor 1
in msmcobalt.
CRs-Fixed: 1010111
Change-Id: I69803580c9f747a0e2e5effa43d33f7a9a0d4e73
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
Enable the LMH hardware and the LMH interface driver.
LMH hardware driver interacts with the LMH hardware and
uses the interface driver to register with thermal core.
CRs-Fixed: 1010120
Change-Id: I2e6f6a181902bee7e3bcb0f366e6ee21f8a4c442
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
Enable kernel thermal driver.
kernel thermal driver can monitor, mitigate and provide interface
to thermal-engine to mitigate.
CRs-Fixed: 1010111
Change-Id: I02b4bc9cf66b2734be99c986d4a200f604145e0a
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
Define the three LMh SW override values per cluster to be used
by the OSM device.
Change-Id: I6279cdbc92d4e0d5786854722474e1dfb14e7198
CRs-Fixed: 1009097
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
To ensure stable operation, it is necessary to place LMh SW override
votes when setting the new rate of the power and performance
CPU clocks. Add support for parsing these values from Device Tree
and programming them in clk_set_rate().
Change-Id: I60d90d546f155edb6c13c46e6c59c75e95848d6c
CRs-Fixed: 1009097
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Update CSC 10 bit YUV2RGB matrix table with appropriate values to
avoid any color conversion issues.
Change-Id: Iaf740873a6814cd9211acf4de4042c7cefecd64d
CRs-Fixed: 997593
Signed-off-by: Ramkumar Radhakrishnan <ramkumar@codeaurora.org>
Add align function to align the values to non power of 2 and align
yuv bitstream plane size and stride appropriately.
Change-Id: I40695e9e7a99fe7c814d26fa7b5205370b7f9f64
CRs-Fixed: 997601
Signed-off-by: Ramkumar Radhakrishnan <ramkumar@codeaurora.org>
LMH lite driver allocates DMA memory for getting the
sensor list from trustzone. DMA memory is not needed for
this operation, so use dynamic memory.
CRs-Fixed: 1010120
Change-Id: Ia7ef920a0f34334e49d76efc5ba233aa58aeb273
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
Thermal core framework allows reading negative temperature and to
support that, thermal core APIs will read temperature in integer.
Inline with thermal core changes, modify the parameters to read
temperature to integer from signed long.
CRs-Fixed: 1010120
Change-Id: I975c11aa4e63e01ee3274a577b51b37c1c0f78cd
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
The permissions of /proc/iomem currently are -r--r--r--. Everyone can
see its content. As iomem contains information about the physical memory
content of the device, restrict the information only to root.
Change-Id: If0be35c3fac5274151bea87b738a48e6ec0ae891
CRs-Fixed: 786116
Signed-off-by: Biswajit Paul <biswajitpaul@codeaurora.org>
Signed-off-by: Avijit Kanti Das <avijitnsec@codeaurora.org>
In some cases modem will delay USB uplink pipe
for flow control. This will happen regardless of
tethering protocol. This change sends a QMI message
to modem to remove the delay on USB pipe in case
of USB cable disconnect.
CRs-Fixed: 1009199
Change-Id: I42cd716dcb87b814256a81418fecdff020f37d9d
Acked-by: Ady Abraham <adya@qti.qualcomm.com>
Signed-off-by: Skylar Chang <chiaweic@codeaurora.org>
Add WCN3990 slimbus slave device tree to support
bluetooth and FM audio.
Change-Id: I15a0abe365555a6695a7317e4d9cfae13a56c49e
Signed-off-by: Sungjun Park <sjpark@codeaurora.org>
Create a new file for hdmi panel related functionalities
for a cleaner approach. Move all the video, infoframe and
timing related programming to hdmi panel. Expose its
functionalities for other modules. Register the panel with
hdmi transmitter core so that it can access and program it.
Change-Id: Iff1cb13d7b42b6ecfe6fd1fc88a111875c3d6cfa
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
The DP RCGs exported by the MMSS clock controller (MMSS-CC)
can be sourced out of the DP PLL which is outside the MMSS-CC. Set up
these external clock sources to point to the DP PLL clocks.
CRs-Fixed: 1009740
Change-Id: Ia8f60ba711770c26e5b5919d2c39d7986403ece6
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Change the feature flag to compile rndis_ipa
on cobalt target with msm-4.4 kernel, also
fix the compile warnings.
Change-Id: I82d3dd00e003d8eab63ca6bcc3bb91d51f122606
Signed-off-by: Skylar Chang <chiaweic@codeaurora.org>
List all the resources needed by the MDSS DP PLL device and add the
corresponding device node for msmcobalt. The DP PLL is the source for
all the branch clocks needed to drive pixel data over the DP interface.
CRs-Fixed: 1009740
Change-Id: I1a373a7602f8dbad3fb547690a87a28aea73aadd
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Add support for new Display-port PLL clock driver to handle
different DP panel resolutions in msmcobalt. Add separate files
to support this new PHY PLL block.
CRs-Fixed: 1009740
Change-Id: Ic282c7e14fc6e23f4d044cb6a58249bdb4c8c2d8
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Set the primary display interface as the DSI device and the preferred
primary panel to be nt35597 dual-DSI (non-DSC) panel on msmcobalt CDP.
CRs-Fixed: 1000724
Change-Id: I8caa21c7b6a5f1e57cbd4c2bffeaa34e1e59d9c2
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
MSMCOBALT supports SLIMBUS_7 RX/Tx and SLIMBUS_8 Tx ports.
Add these ports to the CPU DAI list for passing to machine
driver.
Change-Id: I91306af6a2376fc76d51c62497e9723e6ec716e1
Signed-off-by: Banajit Goswami <bgoswami@codeaurora.org>
Support for SLIMBUS_7 and SLIMBUS_8 Rx/Tx ports added to MSM audio
drivers. Add the right devices to probe/register these ports with
kernel at device bootup.
Change-Id: Id28b3d2fc5db4ec88ddbfa20b36047804d1fbdb6
Signed-off-by: Banajit Goswami <bgoswami@codeaurora.org>
New sequence print functions doesn't return error on overflow.
Use the new API to check for overflow and then return error
from LMH interface driver.
CRS-FIxed: 1010120
Change-Id: I12c496f3c72398845a9039607b27112196afe38a
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
KTM has support for handling cluster with asynchronous cores within
a cluster. KTM can get the individual clock plans for the cores and
mitigate them separately. This feature is not supported in
hardware.
So remove the asynchronous cluster support from KTM.
CRs-Fixed: 1010111
Change-Id: I13348a16e2e1c11053cf5b99b921fd8ea65c7d89
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
When driver detects that there is a dynamic resolution change
mid-stream it will not activate dcvs.
CRs-Fixed: 1007339
Change-Id: Ia5e5b42598b7e32360267e42665a5ce3880aaeee
Signed-off-by: Rohit Kulkarni <rkulkarn@codeaurora.org>
In order to centralize IPA assert calls and add essential
data on assertion, replace some BUG calls in an ipa_assert wrapper.
CRs-fixed: 1006564
Change-Id: I6a9b679bb083c695908972b377e8779e2f1cca60
Signed-off-by: Amir Levy <alevy@codeaurora.org>
Incorrect voltage and temperature results are seen
during ADC reads from VADC_HC peripheral.
Fix setting the correct flag used to select the respective
peripherals scaling formula to return the correct voltage
and temperature readings for VADC_HC peripheral.
Change-Id: I6f4fe857996c8df996b6e4a0e4475a48740929fa
Signed-off-by: Siddartha Mohanadoss <smohanad@codeaurora.org>
If process_open_event is delayed and glink has migrated to new transport,
process open event will be treated as a new open event and migration will
happen on fully open channel.
If channel is fully, open migration will not be allowed as client might
already be using the channel for communication.
Change-Id: I6c1760bc19f52e7d0c1c9834a72e2304f0ae28c8
Signed-off-by: Dhoat Harpal <hdhoat@codeaurora.org>
Add programming support for the qspi_ref and qspi_ahb clocks
in the linux clocks driver.
CRs-Fixed: 1011840
Change-Id: Ic67b72b1e9341fec33bcdbde67f9e2c7e8045ec1
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Add machine driver code to support audio on MSMCOBALT based
boards with WCN3990 BT/FM chipset.
Change-Id: Ia23572f44775a04c8f8c67e9a61d6b9be8869b82
Signed-off-by: Banajit Goswami <bgoswami@codeaurora.org>
Add a new mixer control for volume control for SLIMBUS_8_TX AFE port
loopback.
Change-Id: Ifbf1778255edbe4901bd0860216ba1dd5a786047
Signed-off-by: Banajit Goswami <bgoswami@codeaurora.org>
SLIMBUS_7 and SLIMBUS_8 would be used for BT-SCO and FM use
cases when using the second Slimbus instance. Add routes
to support voice call over BT-SCO and FM playbacki and capture
with these ports.
Change-Id: I5c558ee2dbe2de20b9ac3f042ae45a9431590778
Signed-off-by: Banajit Goswami <bgoswami@codeaurora.org>
SLIMBUS_8 ports can be used for hostless audio playback and
capture use cases. Add Hostless Front-end DAI definitions
with Slimbus 8 ports.
Change-Id: Idc56625bb8fea263c3d530c8a9488eeb81fdd7e5
Signed-off-by: Banajit Goswami <bgoswami@codeaurora.org>
Add support for SLIMBUS_7 and SLIMBUS_8 Rx and Tx ports for
MSM audio drivers.
Change-Id: I839ac07a3ee1e1e778c4d1e43d0bac89f01bd21a
Signed-off-by: Banajit Goswami <bgoswami@codeaurora.org>
Increase the OSM LLM frequency and voltage vote hysteresis timers
to the maximum allowed value of 327675 ns. This is necessary
to ensure stable operation when LLM port is enabled as client of
OSM.
Change-Id: I6b53b5a6187f0ac0e68f4ed54c7ae3ba0b062222
CRs-Fixed: 1009097
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
OSM clock period is 5 ns. Therefore, the various hysteresis
timers used by OSM can be fine tuned with a granularity of
5 ns. Allow specification of timers in units of nanoseconds
to prevent losing valid timer setpoints.
Change-Id: Ice93347aaf81fe41ea7862752ac0d2d4e82d838c
CRs-Fixed: 1009097
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Fix overwrite of updt_params allocated in heap, and stack overread
where param pointer is passed from user space.
CRs-Fixed: 989628
Change-Id: Ida8bdb7da2fcb97023dce3b6eafe4b899a51cb66
Signed-off-by: Weiyin Jiang <wjiang@codeaurora.org>
Increase the refcount of CPU clocks proportionally to the number
of available CPUs to maintain the assumption that each CPU clock
has been prepared and enabled by the time cpufreq takes over.
Change-Id: Icccb28bc7a88dc76cf4ed5710623e992ba62f19c
CRs-Fixed: 994035
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
