Support initializing different registers for sequencer operation
based upon the msmcobalt chip revision. Update the boost and
droop FSM timers to match the latest hardware guidelines.
CRs-Fixed: 1064242
Change-Id: I7e670e6cf1583e5cd97add65106d9964509f2686
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Update the CPR corner switch delay time for the CPRh device
on msmcobalt v2 according to the latest hardware guidelines.
CRs-Fixed: 1064318
Change-Id: I08a385b360d9d0184fd7339194630d8f75a6676f
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Add stub regulator devices for msmfalcon because RPM regulator
support is not yet in place.
CRs-Fixed: 1056821
Change-Id: I6845ed3863ab98a06829372ff1a3d460680def30
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
Re-enable CONFIG_QCOM_REMOTEQDSS for all supported 32bit
targets i.e. msmcobalt and msmfalcon. It was earlier
disabled due to a build issue which is fixed by 'commit
8ecaa617d5 ("soc: qcom: remoteqdss: Fix build error
on 32bit")'.
Change-Id: I4f8302385010cf2e5c3d9baa717bd2d7d1237853
Signed-off-by: Shiraz Hashim <shashim@codeaurora.org>
The current api which performs the clock reset is moved to use the reset
framework, so support the changes in USB driver for the same. The reset
framework requires to get reset handle and perform assert/deassert of the
resets.
Change-Id: Ifcde1c6af624294cbd1944eaa9b526dd6dcc51de
Signed-off-by: Amit Nischal <anischal@codeaurora.org>
Read the charger die temperature and its threshold from RR_ADC,
and expose to the userspace through battery PSY.
Read USBIN current and voltage from RR_ADC, and expose to the
userspace through USB PSY.
CRs-Fixed: 1050042
Change-Id: I452a050298a6ab081f64aa2dcf295d2d257bcb32
Signed-off-by: Harry Yang <harryy@codeaurora.org>
Add support to measure the perf and power cluster clocks
via the debug mux on MSMCOBALT.
CRs-Fixed: 1059153
Change-Id: I1682481dfe22deef300ea9bd1db558ae634c9129
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Add support for ARCH_MSMTRITON in msmfalcon arm64
defconfigs.
Change-Id: Ic83fe1607d5f62e0ceefd4497aae0c111a2727d7
Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org>
Add device tree files necessary to support msmtriton SoC.
Also, add support for Rumi platform.
Change-Id: Ia18a2f53fc3bf7ca459182dc197ad6a2078c7f5c
Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org>
Use the no-log variants of the read{b,q,l}/write{b,q,l} APIs
to prevent flooding the MSM register trace buffer (RTB) logs
with memcpy/memset induced logging.
Change-Id: I16556e1d6f4abe00e6f33b8375a5a1839dfca34e
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
Add the VDD_APC CPR corner configuration corresponding to
speed-bin 1 parts whose performance cluster can operate
at a slower maximum clock rate compared to speed-bin 0 parts.
CRs-Fixed: 1057119
Change-Id: I01e2c9c8bafbb2be4c8d312a4212195c2a99f3ac
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Update VDD_APC0 and VDD_APC1 CPR floor and ceiling voltages
of the highest fused corner on msmcobalt v2 parts to
adhere to latest hardware guidelines.
CRs-Fixed: 1057119
Change-Id: Icf06fe334558bfc4e4dedc9b1f18d51c99987966
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Add support for msmcobalt speed-bin 1 devices which can operate
with a performance cluster clock frequency of up to 2.208 GHz.
CRs-Fixed: 1057115
Change-Id: I2c733a1f0ee4baf978c3715aa3bd74a6b46ee6c2
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
On MSMCOBALT, the GPU GX GDSC enable status register must be
polled to see if the GPU (and top level CPR sensors) are powered
before attempting to perform a CPR aging measurement.
Specify the address of this register as well the bitmask and
expected enable state masked register value in the VDD_GFX CPR
device node.
Change-Id: I55d5fb0c799dfec73830e8e97dcff79cd045b29c
Signed-off-by: David Collins <collinsd@codeaurora.org>
