Lock out interrupts during issuing dummy request in timeout to prevent from
a potential deadlock happening.
Change-Id: I986d8c36c839a1dee23761465ad331ffc31dd6ac
CRs-Fixed: 1008319
Acked-by: Che-Min Hsieh <cheminh@qti.qualcomm.com>
Signed-off-by: Yasir Malik <ymalik@codeaurora.org>
Fd is tunneled using userptr memory type to v4l2 rotator
driver. Fd can assume the same value between multiple qbuf but
with the underlying mapping modified. However, v4l2 assumes that
if userptr of the same value are passed in, the underlying buffer
is the same and will bypass memory mapping callback. This will
cause problem for fd tunneling because the obsolete mapping is
used.
To ensure buffer mapping, add buf_finish callback to clear last
fd value before dequeuing buffer back to user client. This will
force the next queue buffer command to invoke memory mapping callback
since the incoming fd value is different from the reset value.
CRs-Fixed: 1084634
Change-Id: I932a58fc633918b151959fcbe320668a87dbc49c
Signed-off-by: Alan Kwong <akwong@codeaurora.org>
Add more information to the debugfs kgsl/proc/<pid>/mem which
will allow memtrack to correctly assign allocated ion buffer
memory to a process. The additional columns show the number of
kgsl_mem_entries which have a usage of egl_image (or) egl_surface.
When attaching a dma_buf to kgsl, use the dma_buf_attachment's
(void*)priv to point back to the kgsl_mem_entry. This makes it
possible to iterate through all attachments on a dma_buf and
gather statistics from each kgsl_mem_entry associated with the
dma_buf.
CRs-Fixed: 1073673
Change-Id: I1ef3bd0da3f74fa41074021699b2226c48bde9c3
Signed-off-by: Santhosh Punugu <spunug@codeaurora.org>
Any driver can use gpio as function, so adding all the gpios
to pingroups.
Change-Id: I4949954c7b546030a4a94c74bb68c2eb4f6d4718
Signed-off-by: Venkatesh Yadav Abbarapu <vabbar@codeaurora.org>
Convert most of the pmfalcon stub-regulator devices to a
rpm-smd-regulator devices. This ensures that requests made for
these regulators are aggregated by the RPM processor along with
the requests from other processors.
Also, add a dummy gfx_vreg_corner regulator until the CPR node
is added.
While at it, rename all regulators names and add pm/pm2 prefix
to differentiate between regulators on multiple supported PMICs.
Also update all clients with new regulator phandles.
CRs-Fixed: 1077493
Change-Id: I95b17de5bf17b62096d2c9d60633b6b30768752a
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
This reverts commit aa484ff4b6 ("scsi: ufs: stub UFS shutdown
handler").
This is reverted so as to enable PON (Power-off Notification).
PON would notify the ufs device of the incoming power-down
so that the device can prepare for the same before
the power to the device is cut.
CRs-fixed: 941978
Change-Id: Idee8691d769218d7e732c9b7f936a2c40946b239
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
The heap buffer pointed to out_buffer and in_buffer are allocated
but uninitlalized. It may cause information leak.
Change to kzalloc instead of kmalloc when allocating kernel buffers
to avoid information leak.
CRs-Fixed: 1087020
Change-Id: I6f9b7a630158355a7f920dcf9cfffe537b1c6a85
Signed-off-by: Meng Wang <mwang@codeaurora.org>
If a protocol converter or HUB or a dongle supports multi-function
to support both displayport and USB simultaneously and exposes
pin assignment D as supported one, prefer pin assignment D to be
configured on the ports.
Change-Id: Ia69987c0e15ec5f15a07ca3a0e44174ab6e5feb9
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
The current generated link rate in software doesn't
consider fractional values. As a result, for few of
the boundary cases, the calculated link rate is not
correct. Fix this by checking for any fractional values.
Change-Id: I3366b70c7e5bfa2a240aa24f1e0c70b54d686721
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Update the FRAC_START3 register settings for 5.4 GHz link
rate in Display-Port PLL driver. This is needed for accurate
link and pixel clock values.
Change-Id: Ib6a0ee570fe2d5a1d43296e792a354ca25b1d82c
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Update the MISC settings register according the color
depth and format. Update the MVID and NVID registers
using the M and N values used to configuring
the DP pixel clock.
Change-Id: I67e08d3491fbb7c0960c463cc8f979238b89d818
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Since usleep_range provides better accuracy in
comparison to msleep. This helps in reducing the
latency of host bus resume.
Change-Id: Id22104b9e5b63153731df9eb55759de9a86128c6
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
A540v1 and v2 both need to enable the LMLOADKILL quirk for the
GPU.
CRs-Fixed: 1036444
Change-Id: I84243578a1ef2f9948f0c9a8c1c00dc6a31eb579
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
Add a quirk to set LMLOADKILLDIS bit in A5XX_VPC_DBG_ECO_CNTL
and clear LMLOADKILLDIS bit in A5XX_HLSQ_DBG_ECO_CNTL registers.
This is done to avoid a VPC corner case with local memory(LM)
which leads to corrupt internal state on A540 and its derivatives.
CRs-Fixed: 1036444
Change-Id: I31008433f19924bb35560d3e35fe0665e73751d5
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
Embedded tputs depend on WAN RX desc size, but, every target
has its own limitations of memory and embedded tputs goals.
So, add parameter to configure WAN RX desc size through device tree.
Change-Id: I28c550058dd990c9c8cd368a2677097c7f057ccd
CRs-Fixed: 1081543
Signed-off-by: Sunil Paidimarri <hisunil@codeaurora.org>
i2c_freq_mode in msm_cci_get_clk_rates is populated from userspace.
Validate to make sure it has valid values. If a large number is sent
from userspace to avoid a buffer over read.
Crs-Fixed: 1086833
Change-Id: I237f60dca3e3dbad4e6188bf047cf7ec5163d159
Signed-off-by: Rajesh Bondugula <rajeshb@codeaurora.org>
Based on the hardware documentation, update the IMA error
handling and clear sequence. In addition, check for DMA errors
and clear it before SRAM transactions begin. Also, check for IMA
hardware status to run the IMA clear sequence during ima_init and
not just based on IMA exception status alone. This is to help
with FG SRAM access to resume again properly in case of an error
encountered.
Change-Id: I583fa51599a1cbbd029cb45c075429730d2e071b
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
When running concurrent video session, there are some possibilities
that CPU may take more than a second to schedule hfi work handler.
In those cases, one of the threads which is waiting for the response
is timing-out.
Increase hw response timeout and power collapse timeout will give
more time for hfi work handler to be scheduled and process the response
messages.
CRs-Fixed: 1086284
Change-Id: I768ef6c941c791af5a45d846fa81d810b831efa5
Signed-off-by: Karthikeyan Periasamy <kperiasa@codeaurora.org>
Current display driver prints warnings and errors within
the mdss spinlock. This causes in random cases to hold the
spinlock for long time when multiple errors are printed;
Fix this by moving the print of warning and error messages
outside of the spinlock.
Change-Id: I09359b528b4742f72a76690930f3d0ed90bb2caa
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
