Enable the watchdog status registers for msmcobalt v2. This
feature must be specifically enabled in the OSM controller
of msmcobalt v2.
CRs-Fixed: 1076523
Change-Id: I1eb5c61037004e200e8f261d6e39b73028f04ab4
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Request the Nominal Fmax as the boot frequency for
each cluster during probe. This is done to ensure reasonable
boot time.
CRs-Fixed: 994035
Change-Id: Ic2dac9bdc1cd9f9b8d236997eba2e63295d6b4c0
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Update the droop timer settings for OSM on MSMCOBALT.
Change-Id: I9398a81738a778dfae5282ef6809a8c2174bd589
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Disable PLL droop detection and update the OSM timer settings
on MSMCOBALT.
CRs-Fixed: 1072855
Change-Id: I1f769f9ff5a0bab594593c3deaec264a9060c28f
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Using memory barriers does not guarantee that the writes will
be completed before moving further unless the memory is marked
as strongly ordered. Use a read instead to make sure that the
previous writes take effect before the read can be processed
and we continue further.
CRs-Fixed: 1074277
Change-Id: Id1ec59664fb457c37dd63df008fbd6c540dffd67
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
The clock driver does not currently use the secure API to write the
APM threshold value. This leads to the value being always left as 0.
Fix the write.
CRs-Fixed: 1074198
Change-Id: I61d8f930f7fe8c3539803a1e9b942095df0b0f86
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
On MSMCOBALT v2, the qcom,llm-sw-overr flag is no longer needed.
This causes an issue where the corresponding array in code is not
filled up but the check to make the writes to the llm register
still succeeds. This leads to us writing 0 to the register
erroneously multiple times. Fix this check.
CRs-Fixed: 1074141
Change-Id: I2dd529a78d06ac08a34546df39cb01ad4c6cb3d5
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
The current OSM framework does not support mapping multiple OSM
clock frequencies to the same CPR virtual corner. Enable this
support and update the current clock DT entries accordingly.
CRs-Fixed: 1070684
Change-Id: I3422848cabf221f497eb91f9aae5905e34ebdc84
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Support initializing different registers for sequencer operation
based upon the msmcobalt chip revision. Update the boost and
droop FSM timers to match the latest hardware guidelines.
CRs-Fixed: 1064242
Change-Id: I7e670e6cf1583e5cd97add65106d9964509f2686
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Add support to measure the perf and power cluster clocks
via the debug mux on MSMCOBALT.
CRs-Fixed: 1059153
Change-Id: I1682481dfe22deef300ea9bd1db558ae634c9129
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Add support for reading a speed-bin fuse for each cluster.
This allows for the selection of different OSM look-up tables
and thus different frequency configurations based upon device
fused values.
CRs-Fixed: 1057115
Change-Id: I9a864a2abb655e26fff5982b592b4f3c5dbfca24
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Support a new OSM sequence which optimizes the number of
instructions required to program MEM-ACC settings and
the APM configuration of the CPUSS. This frees up sufficent
space to implement the DxFSM workaround.
CRs-Fixed: 1043040
Change-Id: I9499497cb558efcf3c73e7145ce65d3f129be696
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Program architectural register 6 with the address of the SPM
core count hysteresis register and architectural register 7
with the up and down core-count SPM hysteresis values. The
sequencer uses this information to ensure stable operation
when CPU retention or power-collapse and cluster collapse
LPMs are enabled.
CRs-Fixed: 1045435
Change-Id: I5e41ce376c694736128ceb051db86f93467fdaea
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Add support to determine the APM threshold corner via open-loop
voltages in the VDD regulator OPP table. The threshold corner
is used by OSM to determine the APM supply for each DCVS setpoint.
The crossover corner is used by OSM to request a specific voltage
during the APM switch transition.
CRs-Fixed: 1021656 1030444
Change-Id: Iac04f6db8e85b3651a33b6c9bff667365cae891d
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Add the architectural space register programming required to
workaround the droop detector and OSM PLL lock detect interaction.
In particular the workaround prevents the OSM sequence and FSMs
from waiting indefinitely for PLL lock in certain scenarios when
the droop detector is active. In addition, the new sequencer is
compatible with 3 levels of ACC settings, thus update the driver
to reflect this.
CRs-Fixed: 1021659
Change-Id: I178fb226f4eec4c188f11e9e868a575c70ad58ae
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Add a panic handler to dump the OS performance state,
program counter OSM watchdog registers, and the APM status
register when the device crashes due to a kernel panic.
These are critical registers that are useful for debug.
CRs-Fixed: 1033031
Change-Id: I2bbf6884cf83457bfb7e5369bb97614bd4beb150
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
The cycle counters are read often by the scheduler to perform
CPU clock frequency estimation. Remove logging the counter reads
to prevent unnecessary logging to the RTBs.
Change-Id: I15e26e4d46d5ee663923d5678fa75878636e6940
CRs-Fixed: 1023437
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Increase the power-collapse and retention FSM exit unstall
timer to 5 us. This timer is used to wait after a core asserts
its request to exit PC or RET.
Change-Id: Icb5c5f219a197a158e00f600e68111ff699062b7
CRs-Fixed: 1023187
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Increase miniumum PLL frequency to 825.6 MHz. This is necessary to
ensure stable operation when OSM engages the droop path to the
PLL.
Change-Id: Ide3309d4dc713892703e2eb5ee33c9db7f990156
CRs-Fixed: 1021593
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Implement clk_osm_get_cpu_cycle_counter() which returns the
running cycle counter value. Register these two functions with
a scheduler-provided callback to allow the scheduler to estimate
CPU frequency without notification. Lastly, setup the cycle
counter to be increased on every rising edge of the XO clock
for improved accuracy.
Change-Id: Ie0f60ca79efc05901a88da13f7a6476f390518a5
CRs-Fixed: 988356
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
When SPM_CORE_RET_MAPPING is set to 1, cores in retention
are treated as inactive by the OSM. However, currently
this register is programmed to 0 when the flag to treat
cores in retention as inactive is specified. Fix this.
Change-Id: Ibc5df71ddd0cfdabf82d3c1e47efca0d88823a2f
CRs-Fixed: 1017123
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Program the PLL test control register for the power
cluster clock in agreement with hardware guidelines.
Change-Id: I102fd544ea0571d31d2ef9232195d4adbddda6d7
CRs-Fixed: 1009203
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
To ensure stable operation, it is necessary to place LMh SW override
votes when setting the new rate of the power and performance
CPU clocks. Add support for parsing these values from Device Tree
and programming them in clk_set_rate().
Change-Id: I60d90d546f155edb6c13c46e6c59c75e95848d6c
CRs-Fixed: 1009097
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
OSM clock period is 5 ns. Therefore, the various hysteresis
timers used by OSM can be fine tuned with a granularity of
5 ns. Allow specification of timers in units of nanoseconds
to prevent losing valid timer setpoints.
Change-Id: Ice93347aaf81fe41ea7862752ac0d2d4e82d838c
CRs-Fixed: 1009097
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Increase the refcount of CPU clocks proportionally to the number
of available CPUs to maintain the assumption that each CPU clock
has been prepared and enabled by the time cpufreq takes over.
Change-Id: Icccb28bc7a88dc76cf4ed5710623e992ba62f19c
CRs-Fixed: 994035
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
The OSM clock is sourced from the LMh RCG. Model this RCG so
that it can be configured properly to provide the OSM a 200 MHz
clock source.
Change-Id: Ib799e8c082977ac226d6bd31ffad8ca63597c0fc
CRs-Fixed: 1007896
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Currently, there is an assumption that the Fmax differs
from the minimum frequency. This is not necessarily true
if the Clock CPU device defines a single frequency. Fix
this by only adding a maximum frequency/voltage pair to
the OPP table if the maximum frequency differs from the
minimum supported frequency.
Change-Id: I6224ecb800bcbca821f42abec43bc57ee701ce80
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Allow child devices to be defined and populated once the OSM
clock device probes. This enables parent and child relationships
across the OSM clock device and any dependent devices.
Change-Id: I0193663d72e05d8227f9814268ec293cfb94bbe3
CRs-Fixed: 994175
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Use secure IO write calls to program the APM crossover corner
and registers 47 and 48 of OSM sequencer architectural space.
Values for these registers reside in the HLOS, but must be
programmed from a secure domain.
Change-Id: I961bde48822adcbfbbb28130f2872104de5c11ce
CRs-Fixed: 992982
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Add a debugfs interface to enable and configure OSM debug trace
packet generation. There are four different supported OSM packet
IDs and two tracing modes. The supported sysfs files and their
corresponding values are:
trace_enable [0, 1]
trace_method [xor, periodic]
trace_packet_id [0, 1, 2, 3]
trace_periodic_timer [1 - 20000000] (us)
Unless otherwised modified through trace_periodic_timer, the
default periodic timer is set to 1 millisecond.
Change-Id: I82b7f78bac7379e9a647b5c8e68c356cd1d5c863
CRs-Fixed: 987787
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Refactor the enablement and parameter initialization of the
supported OSM FSMs. This initialization can be performed
by the clock-osm driver in absence of secure-world
initialization.
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
CRs-Fixed: 992982
Change-Id: Ie2a78394b388b0357459f1778bb7b2d821abde1c
Support an additional column in the OSM look up hardware table
which establishes a mapping between frequency and mem-acc level.
The OSM uses this mapping to program ACC settings which vary
depending upon the performance level. In addition, update the
OSM sequencer and branch instructions to support ACC programming
as part of the clock scaling scheme and define the mem-acc level
associated with each row of the OSM look up tables.
Change-Id: I03e6f189ab0ab6af406a338bd667fb40240d89b3
CRs-Fixed: 981231
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
The default settings of the gcc_hmss_gpll0_clk_src make it
run at 600 MHz. Call set rate on the clock so that its
divider settings can be programmed.
CRs-Fixed: 989118
Change-Id: I49aee860dd3f0f4f7ecb024228f182d126424906
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
The Operating State Manager is a hardware block which deals with
performing voltage and frequency change operations in the CPUSS. Two
instances exist, one for each cluster, in the msmcobalt chip.
Introduce the OSM clock driver to perform the required OSM hardware
block initialization and support DCVS scale requests.
Change-Id: I3e155db5cd580e371ca1791815e4942f442a3d20
CRs-Fixed: 967319
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
