Disable the interrupt during the init sequence to avoid having
interrupts fired for errors and other things that we are not
ready to handle while initializing.
Change-Id: Ic0dedbad972f25586e792478f9c96c4af7c31d17
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Add some new functions to manipulate GPU registers. gpu_read64 and
gpu_write64 can read/write a 64 bit value to two 32 bit registers.
For 4XX and older these are normally perfcounter registers, but
future targets will use 64 bit addressing so there will be many
more spots where a 64 bit read and write are needed.
gpu_rmw() does a read/modify/write on a 32 bit register given a mask
and bits to OR in.
Change-Id: Ic0dedbadb83d3ac46f7e463c9c901d4f94a7bb58
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
There are very few register accesses in the common code. Cut down
the list of common registers to just those that are used. This
saves const space and saves us the effort of maintaining registers
for A3XX and A4XX that don't exist or are unused.
Change-Id: Ic0dedbadb4dccbba284e9badf2f52f3a72594581
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Add helper functions for TYPE4 and TYPE7 ME opcodes that replace
TYPE0 and TYPE3 starting on the A5XX targets.
Change-Id: Ic0dedbad114e28bdbcba55a788c6307b48e14675
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
When exiting low power modes (M3) do not reset
the DB Mode state if DB mode preserve flag is
set for channel.
CRs-Fixed: 1022868
Change-Id: I6557d28afe9d0ac11b76c683ffba76d7d6ffd377
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
In order to avoid being out of sync between MHI client
and MHI host, host shall not reset the doorbell modes for
hardware channels during MHI_M3 state transition abort.
CRs-Fixed: 1023725
Change-Id: I6c742fc968fd57d71a86039bf1f3f65b1362bc90
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
To avoid any race conditions between MHI_M2 state
transition and MHI_M3 state transition lock the
entire MHI_M3 transition using xfer_lock.
CRs-Fixed: 972390
Change-Id: I7c2e1b7b3966dc5fb8bf2f91bce734bbc58c6fd7
Signed-off-by: Tony Truong <truong@codeaurora.org>
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
There are instances when MHI channel context read
pointer can be accessed simultaneously by different
CPU cores. To make sure read pointer updates visible
to all cores, add a memory barrier after completion
of MHI ring operation.
CRs-Fixed: 966338
Change-Id: Ifc8c4cd7595fed9049009c42420a665fb170079f
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
Validate the channel prior to proceeding further.
Unlock spin lock before jumping to error handler.
CRs-Fixed: 1016969
Change-Id: Ie3328f878b582a333ae15f3b950c258ec42fd768
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
Instead of printing enum index convert MHI_STATE
enum to text representation for easier interpretation
of debug logs.
CRs-Fixed: 1012249
Change-Id: I97a9a7ff293c739531d8197334a0f0a35bf20419
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
Possibility exist when handling a DB MODE event another
core to queue a TRE to same channel. During that time
CC ctxt WP may get updated, however DB MODE event thread
still be using a stale WP. Add a lock to synchronize
DB MODE event thread and queue TRE thread.
CRs-Fixed: 1005752
Change-Id: I7f285da8751a867a1c3d651466537368799eb657
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
Bring in refreshed register definitions from the rnndb database.
Change-Id: Ic0dedbaddd22f6ac0b8cfb6184073968569de22d
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
