In the new SDM660 QRD devices, PM660 does not need the hardware
workround that cut-off voltage should be set to 3.7V, so delete
the qcom,fg-cutoff-voltage property.
CRs-Fixed: 2013279
Change-Id: Ica55128a2f426a668b0d43d04424e13672dd78fd
Signed-off-by: Yingwei Zhao <cyizhao@codeaurora.org>
This reverts commit 9f45a559c7 ("ARM: dts: msm:
add sb_4_tx_vi to support VI recording at msm8998")
It is unnecessary to support concurrency of VI sense
recording and speaker protection.
CRs-Fixed: 1113625
Change-Id: I13ee9fd2daed2ad55347c112eeb79a9bfe6495ba
Signed-off-by: Xiaojun Sang <xsang@codeaurora.org>
Add camera node including rear aux and front camera node, also
add corresponding eeprom actuator ois flash and torch node.
Change-Id: I84e3bfa11127ca7808491df728665f74c9222343
Signed-off-by: Pengfei Liu <pengfeiliu@codeaurora.org>
leds-qpnp-flash driver is not supported anymore. Remove it.
Change-Id: Ie2f570bad8171c460b8167f140d71c052ada2b17
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Allocate extra memory for UBWC color format to
prevent out-of-bounds access by hardware.
Change-Id: Iff1e06b4cb16e0a3e41b667eb9334af87d52cfb5
CRs-Fixed: 2013474
Signed-off-by: Vikash Garodia <vgarodia@codeaurora.org>
When stack memory is provided to IPA HW as part of
descriptor it can lead to cache alignment issues.
Make changes to use heap memory whereever applicable.
Change-Id: I666f98cf2ec45a4743db0ab7bc6d2df821cce84a
Acked-by: Chaitanya Pratapa <cpratapa@qti.qualcomm.com>
Signed-off-by: Sridhar Ancha <sancha@codeaurora.org>
Signed-off-by: Utkarsh Saxena <usaxena@codeaurora.org>
If userspace provides a circular list to isp kenrel
driver through an ioctl, then dirver loops forever.
This way the task might hog the CPU in while loop.
To fix this issue, added a preset count to break
the loop after 100 iterations.
CRs-Fixed: 1064608
Change-Id: Ie896fd3da326e5e972266d8004baecf8681aea6d
Signed-off-by: VijayaKumar T M <vtmuni@codeaurora.org>
Signed-off-by: Lokesh Kumar Aakulu <lkumar@codeaurora.org>
While preparing page tables for fastmap, last level ptes
are not being cache cleaned. Fix this.
Change-Id: I97f894b52484d0d223b15090b94c186bba9af734
Signed-off-by: Shiraz Hashim <shashim@codeaurora.org>
SMB1381 acts as a slave charger in SDM630 QRD board. Add device node
to support it.
CRs-Fixed: 2012488
Change-Id: I03803eddc9db5f9bc7901225fa2defd8bcf0e32d
Signed-off-by: Yingwei Zhao <cyizhao@codeaurora.org>
When prefetch is enabled, MDSS HW works on 2 vsync
boundaries i.e. mdp_vsync and panel_vsync. In the current
implementation we are only waiting for mdp_vsync and there
might be scenarios where driver is configuring interface
flush before panel_vsync, which might lead to undefined
behavior in MDSS HW. So add the recommended delays before
and after dfps update to avoid such scenarios.
Change-Id: Idc801f7b63ea85d88949c8ded06fae322f90dbdb
Signed-off-by: Vishnuvardhan Prodduturi <vproddut@codeaurora.org>
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
If DSI SW requests BTA very close to end of blanking or
start of active region and the BTA acknowledgment takes
more then one BLLP time to complete, then it will have side
effects on video timing generator since DSI will not be
receiving pixel data until BTA finishes. So always wait for
video done interrupt and skip blanking to ensure we fall into
active region before sending BTA request. This will
ensure BTA request is always sent during active region.
Change-Id: Ia9e1193f0229df8c552c3ba0287a5a60837ae540
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
For video mode panels, the assumption is that the vertical
blanking region will be maximum of 4 ms and hence, we wait for
4 ms before queuing the DSI DMA commands. With the incell panels
having huge vertical blanking region and dynamic fps feature,
this assumption is no longer safe. Update the wait logic by
calculating the vertical blanking duration.
Change-Id: I69fdc182342493a54d78ae3ce5f4729e17452155
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
Currently BCL LMH algorithm enable request goes for every time BCL
threshold enablement. It needs to be enabled only once. So Enable
BCL LMH algorithm only once.
Change-Id: I94c7326b7730830f71b71c92df21a589ddd2347b
Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
Just after enabling BCL, reading and evaluating current battery SoC
is bypassed. Because of this, during this same time if battery SoC
is less than preset threshold, BCL doesn't mitigate until next battery
SoC change notification comes. Fix battery SoC read and evaluation
path whenever BCL is enabled.
CRs-Fixed: 2007133
Change-Id: I65639ab078875dc3f6940fd1a89201af98e40881
Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
Presently fastmap iommu feature allocates page tables for
full 4GB virtual address space. This can be optimized to
consider virtual address range [base, size] needed by
client and prepare page tables only for applicable
region.
Change-Id: Ie6c23cb8e1702a823567e126f452b1e72d851f71
Signed-off-by: Shiraz Hashim <shashim@codeaurora.org>
