DSS, DISPC, DSI, RFBI, VENC baseaddr can be obtained from platform_get_resource().
This API in turn picks the right silicon baseaddr from the hwmod database.
So hardcoding of base addr could be removed.
Reviewed-by: Paul Walmsley <paul@pwsan.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
Tested-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
All clock management is moved to dss platform driver. clk_get/put APIs use
dss device instead of core platform device.
Hwmod adaptation design requires each of the DSS HW IP to be a platform driver.
So the device name is changed from omapdss to omapdss_dss in 2420, 2430,
3xxx clock database files. Now the core driver "omapdss" only takes care
of panel registration with the custom bus.
core driver also uses the clk_enable() / clk_disable() APIs exposed by DSS for
clock management.
DSS driver would do clock management of clocks needed by DISPC, RFBI, DSI, VENC
TODO: The clock content would be adapted to omap_hwmod in a seperate series.
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Hwmod adaptation design requires each of the DSS HW IP to be a platform driver.
So a platform_driver of DSS is created and init exit methods are moved from core.c
to its driver probe,remove. pdev member has to be maintained by its own drivers.
DSS platform driver is registered from inside omap_dss_probe, in the order desired.
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
The TRM tells us to wait for the DSI PLL derived clocks to become
active before selecting them for use. I didn't actually have any issues
which this would fix but according to the TRM it seems to be the right
thing to do.
Signed-off-by: Ville Syrjälä <ville.syrjala@nokia.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
In DPLL4 M3, M4, M5 and M6 field width has been increased by 1 bit in 3630.
So the max divider value that can be achived will be 32 and not 16.
In 3630 the functional clock is x1 of DPLL4 and not x2. Hence multiplier 2
is removed.
Signed-off-by: Sudeep Basavaraj <sudeep.basavaraj@ti.com>
Signed-off-by: Mukund Mittal <mmittal@ti.com>
Signed-off-by: Kishore Y <kishore.y@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
Clk sources were not initialized, leading to kernel crash, or possibly to
strange behaviour if DSI was compiled in.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
dss_select_clk_source() was rather confusing. Selecting the source with
enums is much clearer.
The clk source selection is also stored into memory, so that we know what
is the selected source, even when clocks are off. This is important during
setup, as we need to what clocks to turn on before the clocks are turned
on.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
Loops checking for certain condition were rather inconsistent.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
Reported-by: Juha Leppanen <juha_motorsportcom@luukku.com>
The core files of DSS2. DSS2 commits are split a bit artificially to
make the individual commits smaller, and DSS2 doesn't compile properly
without the rest of the core commits. This shouldn't be a problem, as no
configuration uses DSS2 yet.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
