Add bluetooth node for msm8998 interposer platform using
msmfalcon QRD. Configure bluetooth power supply based on
the QRD PMIC PMFALCON/PM2FALCON. Disable qca,wcn3990
Bluetooth node to avoid failure in bootup.
CRs-Fixed: 1088153
Change-Id: I00527f465b9251d1329ca3c783cafeafadfce8f2
Signed-off-by: zhenchao <zhenchao@codeaurora.org>
This reverts commit d796ae6e8878daecf855d23658c546aeef506142
("input: powerkey: don't send dummy release event") which was
added as a workaround to ensure that keys held during resume
were not artificially released by the input framework. This
issue is already resolved by commit 768d9aa557
("Input: don't call input_dev_release_keys() in resume").
Change-Id: I542837eddce7cb1ffba55c3e5d6b2e5bd12c9e62
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Debounce delay range and hence the bit encodings got changed in
PON GEN2 peripheral. Fix qpnp_pon_set_dbc() to configure the
debounce delay properly.
CRs-Fixed: 1097089
Change-Id: Ia3d474a04e11c7d16a1507d65e99001cf844947b
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Add initial device tree support for CDP, MTP and RCM
platforms of msmfalcon.
Change-Id: I2e4591c50fe3db61ed3a4364647579bf254d0edd
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
LCDB supports the LCD display +ve/-ve bias. Add the device
node for it.
While at it, disable the LCDB module for PM3FALCON and remove
the dummy bias regulator nodes from falcon interposer.
CRs-Fixed: 1074468
Change-Id: I0aa4736aa0f2d6c6fe3b2e0d19c41df80c0975fe
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
LCDB driver exoses regulators to control the positive and
negative voltage bias for the LCD display panel. It also
allows configurability for the various bias-voltage parameters.
CRs-Fixed: 1074468
Change-Id: Id3c0eccd95d5e510489ee74b3043082b7e473daa
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
QPNP LCDB regulator driver supports the LCD display
bias configuration. It exposes 2 regulators to control
the positive and negative voltage biases.
CRs-Fixed: 1074468
Change-Id: I069dc61ee4fc5d56aff2b836f06fa7246285e42a
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
Add the power supplies to vote for max supported voltage on the
regulator for mdss dsi. Also add mdss dsi node for the msm8998
v2.1 interposer.
Change-Id: I84cae6e7816834dfce0839faa41903f2f871782d
Signed-off-by: Ashish Garg <ashigarg@codeaurora.org>
Enable config IP_NF_MATCH_RPFILTER.
This option allows you to match packets whose replies would go out via
the interface the packet came in
Change-Id: I2a23346e726a8df8487aeb664d6316b3cf2b9d77
Signed-off-by: Ashwanth Goli <ashwanth@codeaurora.org>
Triggering Crash Dumper might actually change the values of
few GPU registers including VBIF. Hence dump those registers
ahead and skip them from the list which goes to crash dumper.
Change-Id: I37a53983a65bd8abfefa780053819de71df7f24f
Signed-off-by: Rajesh Kemisetti <rajeshk@codeaurora.org>
By default A5xx GPUs use CP crash dumper to get GPU
snapshot in case of any fault.
At times it is required to disable crash dumper
in case of any abnormalities, add support to do so.
Change-Id: Iea6497778bcd711e769f0e509103bd3bd0fd8574
Signed-off-by: Rajesh Kemisetti <rajeshk@codeaurora.org>
Power regulator pm2falcon_bob is used to supply micbias
to WCD codec. Add the supply in codec supplies list.
As external buck supply is from VPH_PWR, remove
entries of s4 rail.
Change-Id: I24791396fff9bf612985ff2073e2a74356570a35
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
Reduce halt ack timeout to 25 ms from 100 ms to reduce delay in
mss shutdown path.
Change-Id: I935e35d5d848e564aad5987b1652546046f0927d
Signed-off-by: Avaneesh Kumar Dwivedi <akdwived@codeaurora.org>
Add a new RCG clock ops specific for the DP pixel clock source.
Change-Id: I2ec5ddcfd47af8362f76d76d153e30d4e2f45370
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Vote on the CX rail only if the gfx_ldo regulator
is enabled.
CRs-Fixed: 1078568
Change-Id: Ice3a527b9952c0fdee813d8ad152d4c1deea7ecd
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
A few gfx_ldo memory read/write calls use an invalid ldo
base address leading to other corruptions in the system.
Fix this by using the correct LDO base address.
CRs-Fixed: 1078353
Change-Id: I034d473e86b3fe7164d1c9ddad326c9dd77a188f
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
Enable the configuration which keeps the CPR sensors active
when LDO is in auto-bypass mode. The sensors only stay
bypassed when LDO is regulating.
CRs-Fixed: 1027469
Change-Id: I6b8c2a3fd8fe22a64b6d24c458a7c60641195e45
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
Add a DT property to adjust the open-loop voltage for the LDO
corners, this will be useful for voltage adjustments after
LDO characterization.
While at it, update the LDO MIN_VOLTAGE value for 8953.
CRs-Fixed: 1010052
Change-Id: I7479ebbf0ac7253eb355246d36f15a91ce96cd9a
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
Change the LDO_EN bit definition for GFX LDO on MSM8953 and
remove the LDO bypass fusing logic as it is not supported.
While at it, add the debugfs node to disable ldo_mode.
Disable LDO mode: echo 1 > /d/msm_gfx_ldo/ldo_mode_disable
Enable LDO mode: echo 0 > /d/msm_gfx_ldo/ldo_mode_disable
CRs-Fixed: 989270
Change-Id: Ibc7aa921380e89da4963571408b89bc417dec245
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
Remove all reference to internal code name msmtitanium
and replace them with msm8953, as there is an official
announcement for msm8953 SoC.
Change-Id: If99bbf20756a524c5a3bd7ba49366c29e158289e
Signed-off-by: Tirupathi Reddy <tirupath@codeaurora.org>
Enable the PWMs mapped to the RGB module and specify
the lpg-lut-size.
While at it, enable the haptics and flash node.
Change-Id: I83cf7882d1abb96c343973894c2a7ab3f932dfb1
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
Currently one gic interrupt is mapped to one mpm pin.
Support multiple mpm pins to get enabled with single irq
with client drivers using enable_irq_wake API.
Change-Id: Iea575079c24ed0986b74fb6e86c7b8100474f19e
Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
During the GDSC enable sequence, the GDS_HW_CTRL forces some
clocks to be on to trigger the handshake to unhalt the SMMU
and NOC. Once the handshake completes, the controller asserts
the PWR_ON status and disables the clocks.
If the clock driver tries enabling the SMMU ahb/axi clocks
immediately, there is a possibility that these clocks might
still not have gone through their disable sequence; especially
if the AXI/AHB rates are very low. If this happens, the clock
driver falsely assumes that the clocks are on and returns. Any
SMMU accesses/traffic at this point might lead to a failure since
the clock could turn off.
Change-Id: I544ca82e20e1c026d0ff1881c96edd33bf362b7d
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Fix the following in qpnp-power-on driver:
- Use GENMASK for bit mask
- Remove unused module parameter
- Use nested comments properly wherever applicable
- Fix conditional block formatting and typos
- Use const qualifier for of_device_id table
Change-Id: Ib9dd9be6cafad4c7aec1c88d9828ef1ebbe2a1c3
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
The IOVA allocator used by these calls supports IOVA address
zero so properly handle IOVA address zero.
Change-Id: I012452d4cf3534dfb79e6deb15b7ff74f5e3bb40
Signed-off-by: Liam Mark <lmark@codeaurora.org>
The smb138x device has been duplicated across many board level files.
Refactor the smb138x device to a separate dtsi file so it can be
included in any board level files.
Change-Id: I9520595f2a40e197ad2227a8391bed79412b19f8
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
