Currently for RGB666 format, the MDP output is set as LSB aligned
and banding artifacts are observed due to this. Set the MDP output
to be MSB aligned to avoid these artifacts and for the display
to show up fine with RGB666 format.
Change-Id: Id8b7bf03218dd0ea70ada34912afd092e239b89f
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
Right now, writeback QoS registers are being programmed dynamically
when respective paths are being exercised. Starting 8916, wb QoS
is starting to differ from other chip-sets and since these are
chip-set specific settings, hence configure them using device-tree.
Change-Id: I7eb3717e3756f1eb09c0f1e972fc326854b8ee37
Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org>
framebuffer and overlay drivers are tightly coupled with
splash thread functionality. This adds lots of code
related to continuous splash screen handling in
both drivers. Moving them to separate file cleans up
both drivers and allows to handle continuous splash screen
cases efficiently.
CRs-fixed: 605934
Change-Id: Id89bb281dbbf22e726cf5fd97e93f891e5c73f60
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
[cip@codeaurora.org: Moved new file locations]
Signed-off-by: Clarence Ip <cip@codeaurora.org>
Allow the check_status interval time to be
configurable via /sys interface.
Allow the dsi_check_status function to be
enabled or disabled via /sys interface
Combine MDP3 & MDP5 code and separate
the platform specific code.
Change-Id: Ida14b96864353fb58606009bc00312f6f338c736
Signed-off-by: Raghavendra Ambadas <rambad@codeaurora.org>
[cip@codeaurora.org: Moved dsi_status_6g.c file location]
Signed-off-by: Clarence Ip <cip@codeaurora.org>
Each MDP source pipe can generate 4 levels of priority
and those priorities are remapped before reaching the
AXI bus. These re-mapper settings depends on the chip-set
and the nature of the control path source pipe is used
in. Ex. re-mapper value for DMA pipe used in DSI,
real-time control path, will be different than DMA pipe
used in rotator, non-real-time control path. Provide
support to implement this configuration.
Change-Id: I254f76dd47e3c41adde9894a23232e2f83e6b79c
Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org>
Unblock overlay_set, prepare and buffer sync ioctls when
commit thread finishes hardware programming.
Use wait_for_kickoff instead of pan_idle for these ioctls.
CRs-fixed: 620740
Change-Id: Iefb6cbc390d2130926fdcb93688b4d92bfb26937
Signed-off-by: Ken Zhang <kenz@codeaurora.org>
The correct AVI infoFrame packet type code is 0x82 which is
0x80 + InfoFrame type code. InfoFrame type code for AVI InfoFrame
is 0x2. This should be properly filled in to avoid checksum error.
Change-Id: I9f5acbd2bf2c98908eb214c2d9af02a9c35332a7
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
Program scalar registers for both RGB and VIG pipes
when requested by the user. The scalar factors are
also computed by the user.
Change-Id: I6854a9ff3acdef07bb6a964f2f3686612230eff3
Signed-off-by: Sree Sesha Aravind Vadrevu <svadrevu@codeaurora.org>
Mdp spin lock is used in dsi_event_thread and in irq context.
Disable irq while holding spinlock to avoid context switching
into irq context and cause spinlock recursion
CRs-fixed: 652850
Change-Id: I4bd8cadb1f5d83acc7e866344b7585e7944e08ac
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Turn off the backlight while shut down panel as it
could show white flicker depending on the panel.
Change-Id: Ic5d4e97e70c87e5b6e956e27a766136610d6f345
Signed-off-by: Shuo Yan <shuoy@codeaurora.org>
There may be need to fine-tune the te parameters depending on
panel. Move te parameters to panel dtsi file so that this can
be configured from panel dtsi file.
CRs-Fixed: 616178
Change-Id: I465b96f1631a96cddfa15c9c3004e3dbdcea5982
Signed-off-by: Shivaraj Shetty <shivaraj@codeaurora.org>
In certain dual-dsi products it is possible to physically attach
left-panel on DSI1 interface and right-panel on DSI0 interface. This
particular configuration requires MDSS to swap its output going into
these two interfaces. Current implementation achieves this by swapping
pipes across two layer mixers (LMs) but that solution is not scalable
and optimum when used with source split. We can achieve the same results
by using crossbar located before MDSS interfaces which will allow ctl0
to send data to DSI1 and ctl1 to DSI0. This new implementation is
minimalist and scalable. Implement this new method by swapping interface
assigned to ctl path.
CRs-Fixed: 651286
Change-Id: I7a435f81bd42c197e2eb8655882da9352c091c09
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>
DMA allocation API requires a non-null device
for DMA buffer allocation. This allows for
device specific book-keeping of DMA buffers.
Pass the DSI controller device for such allocation.
Change-Id: I37695bbe7481a2d842fb705a5ef567dbb9049de3
Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org>
Signed-off-by: Manoj Rao <manojraj@codeaurora.org>
The rules applied to switch formats must be the same across
rotator output and the following pipe setup. Also, yuv rotator
output format should always be set to pseudo planar for MDP
hardware optimality.
Change-Id: I3f5f09bcc599627e47495fab253ec0d9d8d5fa1c
Signed-off-by: Sree Sesha Aravind Vadrevu <svadrevu@codeaurora.org>
At current broadcast mode implementation, dsi-1 try to clear dsi-0
irq at its interrupt service routine. This is not necessary.
When broadcast enabled, dsi-0 fetch command and wait for dsi-1 to
trigger cmd engine so that both dsi-0 and dsi-1 dcs commands are sent to
destination synchronously. Both controller receive CMD_DONE isr to
indicate dcs commands had been sent to destination. Therefore both
dsi-0 and dsi-1 should will clear its irq.
CRs-Fixed: 651042
Change-Id: Idd2ff593f8ab8b514bf760090b98aaaf4dd4429a
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
When PREPARE OVERLAY ioctl returns an error code to indicate
reason for failure, the compat layer must not overwrite this error
code with those from compat functions. Userspace processes calling
overlay ioctls rely on error code from driver ioctls, not the error codes
from compat functions for some use cases Ex: falling back to mixed mode
composition on -E2BIG.
Fix this by propagating appropriate error code on failure.
Change-Id: Ib238437be58731724a445f90183511011a6e612c
Signed-off-by: Manoj Rao <manojraj@codeaurora.org>
In mmap implementation for mdss-fb, the argument for page protection
flags were used only in the legacy MDP drivers. Remove these
these unused flags.
Change-Id: I5d67008b5b61165d2cc87ac15e5ef544dcdf819f
Signed-off-by: Manoj Rao <manojraj@codeaurora.org>
Currently core clock is calculated for each frame and
depending upon the calculated value clock driver rounds it
to the nearest clock level from clock table. Now do
quantization of required clock rate at mdp driver itself
once before the request goes to clock driver.
Change-Id: Ie30947fb8f7d2978bb121b28920c05888332bf3f
Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org>
Allow only retrieval of pipes that are on particular framebuffer device
used list. This ensures that pipe is not modified from a different fb
device node and cause potential issues.
Also, modify the ref count logic to use kref and ensure pipe is freed
only while holding mutex in case there could be race condition that
pipe is allocated while being freed.
Change-Id: I626323b5df981a7ed1e03196126cd4376b5ba6a6
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
For every pipe get/map call there needs to be a related unmap call.
These are missing in some cases.
Change-Id: I85f8897be6d34ef217102ef922a48afb6e6cc838
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
If underrun occurs in dual pipe mode (edp, or HDMI) then
there is a chance the 3d_mux will get confused and route
right to left and left to right. This will happen if it
is on the right side when the underrun condition happens.
To fix this following steps are required:
- Disable HW recovery
- When underrun is detected, wait for vsync.
- Issue sw_reset to the ctl path.
This is required to cleanly reset the 3d_mux in case the
swap has occurred.
Change-Id: I8fbf747da4720c12d48bc1ee431bab6224148e31
Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org>
When the first histogram kickoff is done past reset, it might
be too late into the waiting period of completion. This
would cause a timeout even though data for the frame is made
available and interrupt is generated after timeout. This
causes a histogram read call to return with an error and
delay reading the data.
Edit to make the wait for ready to start after the first
kickoff. Add additional completion to denote first kickoff
and start wait after first kickoff wait has completed.
Change-Id: Ic9156b4d8852520715324707290287eb09df6195
Signed-off-by: Krishna Chaitanya Parimi <cparimi@codeaurora.org>
MISR register configuration has moved to individual
blocks in msm8916. Address the same by properly taking
care of Register offsets.
Change-Id: I7cf1c1c38e85db3b2a5ab8d5cb66ae54db7ae6e0
Signed-off-by: Vishnuvardhan Prodduturi <vproddut@codeaurora.org>
Adding params in debugfs to tune the performance of the driver
at runtime from debugfs. These params are min_bus_vote,
clk_factor, ab and ib factor, bw thresholds etc. User can tweak
these parameters from debugfs to help in debugging the issues.
Change-Id: Ie134eba35bf81ecc1524fba29bae902870673bd0
Signed-off-by: Vineet Bajaj <vbajaj@codeaurora.org>
This is to avoid kernel recompilation when a different
framebuffer split ratio is desired at run time. To
enable a new ratio, write the desired value to
/sys/devices/virtual/graphics/fb0/msm_fb_split.
Changes will take effect only after client releases
all references to driver.
Change-Id: I4764399f80fc22ec5815a8e2818901189b3aaeb5
Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org>
When updating the pipes for all the stages during the pipe
update, we need to consider the first enum so the rotator
is considered; otherwise bandwidth calculations does not
add the contribution of the rotator for the final
bandwidth calculation.
Change-Id: I970e6dcbf3dc37819135bc4d632858f3ebc486bf
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
clk_prepare got moved inside mdp3_clk_update. Prior to this patch
unprepare would never be called successfully.
Change-Id: I28ab035b42d433f379d63748ac4f506a8575ea66
Signed-off-by: Terence Hampson <thampson@codeaurora.org>
When rotator is used, write-back interface is used to write data back to
memory. When wait function for write-back is returned, it will remove its
vote for mdp clocks. So during command mode panels, it is possible that
rotator is used without panel itself being turned on. In this scenario
register access after wait function leads to un-clocked access and L2
kernel panic. Fix this by voting for mdp clks before any register
accesses following wait function.
Change-Id: I9b248d39132f197fc8abd23ab3a23a9eb105ba22
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>
Add compat layer for OVERLAY_PREPARE ioctl
implementation in MDSS driver. This allows
for 32-bit user process to call the prepare
ioctl in a 64-bit kernel.
Change-Id: I4effef4e43184b9eeb9054447d99ba9adb5f3857
Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org>
Signed-off-by: Manoj Rao <manojraj@codeaurora.org>
copy retire fence fd in the buf sync structure as a part of
buf sync compat ioctl implementation. This fd is an essential
part of the buf sync implementation that needs to be included
in the compat layer.
Change-Id: If60b5f9115ccb128bc7b56a735b06c31fa0e47f6
Signed-off-by: Manoj Rao <manojraj@codeaurora.org>
MDP control path needs to be restored whenever MDSS GDSC is turned
back on while exiting the utlra-low power state (ULPS). Hold a
reference count for the MDP clocks to ensure that there is no
unclocked register access.
Change-Id: Ia2d299d9db9c23e4c9171cbec8e376908046494b
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
The TE GPIO needed on command mode panels has a gpio_func
value of 1. Acquiring resources of this gpio using gpio_request
API might configure this to a common gpio which has
gpio_func value equal to 0. Hence control this gpio using
the gpiomux framework.
Change-Id: I2e14ada484a6d20774030393ae6549f05ac1e8db
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
On 8916, there is no support for MMSS MISC AHB clock. Hence, if clk_get
fails for this clock, do not fail DSI probe since this is expected for
this target.
Change-Id: Ifaed8588d88f1daeb07ad4392592c12abb982001
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
For single layer use case, mdp prefill bandwidth request can be
reduced because mdp pipe operates like a fifo and there is no need to
fill all buffers before the active region.
Change-Id: Ic087f394b2551658543cff7f99789eace0388e07
Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
When clock enable fails, the error handling logic should ensure
to remove the reference counts for the master controller clocks only
if the master controller is valid. Add the necessary checks to ensure
this so as to avoid any null pointer dereferences.
Change-Id: If2779c4febe19d882a8247872de6fac94f5b0ded
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Previously, the change of backlight sysfs node value will not trigger
notify updates if display is in static screen case. This will cause
delay or wrong configuration for assertive display. This patch fixes
the above issue by adding an update notify if backlight changes when
there are no display updates.
Change-Id: I1475896214a50dc1fa71739aa751b2e626d27adb
Signed-off-by: Ping Li <quicpingli@codeaurora.org>
Current design of display driver (overlay) is no more
using the physically contiguous memory for normal display
functionality.
However, we still need to be backward compatible for any client
using the legacy implementation (eg. pan display) functionality.
As soon as there is a mmap call, the allocation happens from
system heap and gets removed once the references to frame buffer
driver becomes NULL.
With this change one can remove the physically contiguous memory
which gets allocated at the boot time and the usage of physically
contiguous memory is optimized.
Change-Id: I1b6040187bda8095007faa4d9df7dc046aa30c6e
Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org>
In APQ8084, when BWC is enabled and source dimension of the pipe are
changed then MDP ahb clock gating needs to be disabled. Now once this
condition has passed, clock gating needs to be enabled again to save
power. Current implementation writes wrong value to the register which
handles this clk gating. The same register is used for controlling clock
gating of other source pipes like VIG1, RGB1 & DMA1. Because of this
wrong value, pipe was being forced off which internally results into
under-runs. Fix this issue by writing correct value in the clock gating
register.
Change-Id: I2f5568a1a90e4384da14fcee5a21494841c12ae6
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>
This makes sure that the userspace correctly interprets the end
of the vsync timestamp.
CRs-Fixed: 639039
Change-Id: I8a0810283a42a9c39a3c8fe36b862bbfd3ecdbea
Signed-off-by: Shivaraj Shetty <shivaraj@codeaurora.org>
Currently different drivers within MDSS, allocate dynamic memory using
kmalloc and then use explicit memset to zero out the content. Instead use
kzalloc API to achieve the same.
Change-Id: I09d3d5e5986206f90c97d4d04fc3a855c233a7ae
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>
Add panel ROI limitations on minimum width and height values
to the panel info sys_fs node.
Change-Id: I3297beb20e7f207a296e6cec114daf2305324898
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Grouping calls to prepare and unprepare of clocks along with enable
and disable for saving power in the case of static screen on command
mode panels. This makes sure that corresponding source clocks are
also disabled allowing xo shutdown to happen.
On top of that bandwidth request and iommu enable was grouped with
enabling/disabling clocks so that all display related clocks are
disable in static screen allowing for xo shutdown to happen.
Change-Id: I2db3844cbab5c41ea1bb37f5a5ed76c3c63e3a1d
Signed-off-by: Terence Hampson <thampson@codeaurora.org>
If handoff fails, the clock ref count becomes 0 and iommu
will get detached. In pan display path, since at that
particular instant iommu gets detached, we use physical
address. After this if iommu is again attached and physical
address is fetched, it can result in continuous IOMMU page
faults. To address this hold MDP clock ref count
in pan display path.
Change-Id: I2370b276acdced2cf22083eb80fcad1b2e454315
Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org>
Update the AD init compact structure with backlight attenuation
support.
Change-Id: I25cf939994d5138f1accf93b8f4bc130bd7ca59e
Signed-off-by: Ping Li <quicpingli@codeaurora.org>
Pinctrl needs to be set to active state before we do the panel
reset during panel ON sequence. Similarly, it needs to be set to
suspend state after the GPIO IN_OUT registers are set to zero.
This change takes care of fixing this sequence.
Change-Id: I666068f88d4489acb0da261efb01e26929e42483
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
This adds the underflow color adjustment support on
8x10. Customer can order underflow color by modifying
the parameter in panel device tree.
Change-Id: I5a0ae73bceff26b810de6809beb540681c30247f
Signed-off-by: Shuo Yan <shuoy@codeaurora.org>
Overlay release allows multiple releases to happen by having
multiple bits set in overlay unset call. Fix logic to find
all pipes which match the bitmap.
Change-Id: I6a25a81fe4c437b5546537d48e250055357682f0
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>
We were dereferencing a userspace pointer in kernel.
Change-Id: I128455904cd396690350fc6b784a8844d594539c
Signed-off-by: Terence Hampson <thampson@codeaurora.org>
Changing the error log to debug log in case SMP reserve fails
for rotation. The use case falls back to GPU. Same is being
done in case of mdp interface set path.
Change-Id: I00a9e05b3a04a87e354fd0e60ad900f4f71cdfc1
Signed-off-by: Vineet Bajaj <vbajaj@codeaurora.org>
