The uart pdata array is already terminated by a zero flag field.
This patch reuses this terminator and eliminates DAVINCI_MAX_NR_UARTS
definition. This way, future platforms can have different number of uarts
initialized via davinci_serial_init().
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
The earlier watchdog reset mechanism had a couple of limitations. First, it
embedded a reference to "davinci_wdt_device" inside common code. This
forced all derived platforms (da8xx and tnetv107x) to define such a device.
This also would have caused problems in including multiple socs in a single
build due to symbol redefinition.
With this patch, davinci_watchdog_reset() now takes the platform device as an
argument. The davinci_soc_info struct has been extended to include a reset
function and a watchdog platform_device. arch_reset() then uses these
elements to reset the system in a SoC specific fashion.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Tested-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Pinmux registers are sequential, and do not need to be enumerated out as they
currently are. This reduces code volume and keeps things simple.
If some future SoC comes up with a discontiguous register map, PINMUX() can
then be expanded with local token pasting.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This patch eliminates the global gpio_lock, and implements a per-controller
lock instead. This also switches to irqsave/irqrestore locks in case gpios
are manipulated in isr.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Tested-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This patch allows for gpio controllers that deviate from those found on
traditional davinci socs. davinci_soc_info has an added field to indicate the
soc-specific gpio controller type. The gpio initialization code then bails
out if necessary.
More elements (tnetv107x) to be added later into enum davinci_gpio_type.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Tested-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This patch renders the inlined gpio accessors in gpio.h independent of the
underlying controller's register layout. This is done by including three new
fields in davinci_gpio_controller to hold the addresses of the set, clear, and
in data registers.
Other changes:
1. davinci_gpio_regs structure definition moved to gpio.c. This structure is
no longer common across all davinci socs (davinci_gpio_controller is).
2. controller base address calculation code (gpio2controller()) moved to
gpio.c as this was no longer necessary for the inline implementation.
3. modified inline range checks to use davinci_soc_info.gpio_num instead of
DAVINCI_N_GPIO.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Tested-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Renamed gpio types to something more sensible:
struct gpio_controller --> struct davinci_gpio_regs
struct davinci_gpio --> struct davinci_gpio_controller
gpio2controller() --> gpio2regs()
irq2controller() --> irq2regs()
This change also moves davinci_gpio_controller definition to gpio.h.
Eventually, the gpio registers structure will be moved to gpio.c and no longer
a common cross-soc definition.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Tested-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
The IDE platform device is registered in three different places (2 board files
for DM644x and in dm646x.c for DM646x) while both the IDE base address and the
IDE IRQ are the same for both SoCs -- therefore, the proper place for the IDE
platform seems to be in devices.c. Merge the IDE platform data and registration
code and create davinci_init_ide() in place of dm646x_init_ide()...
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
linux/compiler.h is required for __iomem
linux/types.h is required u32
Signed-off-by: Thomas Koeller <thomas.koeller@baslerweb.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This patch allows socs to override the divider ratio mask by setting an
optional field (div_ratio_mask) in the pll_data structure.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Tested-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Extended the MUX configuration to allow use of GPIO
terminals 64..57.
Signed-off-by: Thomas Koeller <thomas.koeller@baslerweb.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
The board file #define's its own version of EMIFA base addresses, while there
are DA8XX_AEMIF_*_BASE macros #define'd in <mach/da8xx.h>. Start using them
instead.
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Currently each DaVinci board file #define's its own version of the EMIFA base
addresses (all named DAVINCI_ASYNC_EMIF_*_BASE), which leads to duplication.
Move these #define's to the SoC specific headers, changing their prefixes from
'DAVINCI' to the 'DM355', 'DM644X', and 'DM646X' since all these base addresses
are SoC specific...
And while at it, rename DM646X_ASYNC_EMIF_DATA_CE0_BASE to
DM646X_ASYNC_EMIF_CS2_SPACE_BASE in order to match the DM646x datasheet.
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Added tnetv107x cpu type definitions and cpu identification macros.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
IRQ numbers as defined for tnetv107x cp_intc.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Added definitions for LPSC modules in the tnetv107x SOC
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Added list of muxed pins on the tnetv107x SOC.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Rename da8xx_pinmux_setup() to davinci_cfg_reg_list() and promote it for use in
other SOCs that may need the ability to configure multiple pins in one shot.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
The current clock control code always gates the clock (PSC state Disable = 2)
on clk_disable(). Some on-chip peripherals (e.g. LCD controller on TNETV107X)
need to be put into SwRstDisable = 0 on clock disable, to maintain
hardware sanity.
This patch extends the davinci_psc_config() arguments to pass in the desired
module state instead of a boolean enable/disable. Further, clk_disable() now
checks for the PSC_SWRSTDISABLE clk flag before selecting the target state.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Host map configuration instructs the interrupt controller to route interrupt
channels to FIQ or IRQ lines. Currently, DA8xx family of devices leave these
registers at their reset-default values.
TNETV107X however does not have sane reset defaults, and therefore this
architecture needs to reconfigure the host-map such that channels 0 and 1
go to FIQ, and the remaining channels raise IRQs.
This patch adds an optional host map argument to cp_intc_init() for this.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
timer_init() programs timer64 hardware. The module should ideally be brought
out of reset before this happens.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Preliminary modification prior to adding support for TNETV107X based on
ARM1176. This change allows for CPUs other than ARM926T to be used for Davinci
derivative SoCs. Existing devices (DA8x and DMx) operate unchanged.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Currently, the ISR in the EDMA driver clears the pending interrupt for all
channels without regard to whether that channel has a registered callback
or not.
This causes problems for devices like DM355/DM365 where the multimedia
accelerator uses EDMA by polling on the interrupt pending bits of some of the
EDMA channels. Since these channels are actually allocated through the Linux
EDMA driver (by an out-of-kernel module), the same shadow region is used by
Linux and accelerator. There a race between the Linux ISR and the polling code
running on the accelerator on the IPR (interrupt pending register).
This patch fixes the issue by making the ISR clear the interrupts only for
those channels which have interrupt enabled. The channels which are allocated
for the purpose of being polled on by the accelerator will not have a callback
function provided and so will not have IER (interrupt enable register) bits set.
Tested on DM365 and OMAP-L137/L138 with audio and MMC/SD (as EDMA users).
Signed-off-by: Anuj Aggarwal <anuj.aggarwal@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
CC: Archith John Bency <archith@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
The merge for 2.6.34 brings in 8-bit support to the DaVinci MMC/SD driver.
This patch updates the platform data for DA830/OMAP-L137 EVM to use 8-wire
support available in the driver.
Signed-off-by: Vipin Bhandari <vipin.bhandari@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
The DA830/OMAP-L137 EVM has GPIO based card detection logic, but the current
code does not use it.
Add support for GPIO based card detection to avoid reading the card to see
if a card is present or not.
Signed-off-by: Vipin Bhandari <vipin.bhandari@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Cleanup usage of void pointers when using genirq. genirq API
takes and returns void *, where this GPIO API is using those
as __iomem pointers.
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Add clocks with appropriate names in platforms that use it, and use the
clk API in nomadik-gpio.
Acked-by: Alessandro Rubini <rubini@unipv.it>
Acked-by: Linus Walleij <linus.walleij@stericsson.com>
Acked-by: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add a table for clocks to be defined statically, so that new clocks can
be added without having to call nmdk_clk_create() for each of them.
Remove the now unused nmdk_clk_create() function.
Acked-by: Alessandro Rubini <rubini@unipv.it>
Acked-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Set a default trigger type for interrupts, otherwise if request_irq is
called without specifiying a trigger type, the interrupt will not
actually be enabled.
Acked-by: Alessandro Rubini <rubini@unipv.it>
Acked-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
On this peripheral, setting the trigger type enables the interrupt, and
the current set_type() implementation unconditionally enables the
interrupt, even if it is called when the interrupt is disabled. Fix
set_type() to:
- if the interrupt is disabled, defer the actual trigger setting to
when it is unmasked
- if the interrupt is enabled, change the type immediately by clearing
the old type and then re-enabling with the new type.
Acked-by: Alessandro Rubini <rubini@unipv.it>
Acked-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Remove some nearly-duplicated code to make the following patch simpler.
Acked-by: Alessandro Rubini <rubini@unipv.it>
Acked-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Mask/unmask should modify the interrupt mask register (RIMSC
and FIMSC) not the wakeup mask registers (RWIMSC and FWIMSC).
Acked-by: Alessandro Rubini <rubini@unipv.it>
Acked-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Reimplement stop_machine using cpu_stop. As cpu stoppers are
guaranteed to be available for all online cpus,
stop_machine_create/destroy() are no longer necessary and removed.
With resource management and synchronization handled by cpu_stop, the
new implementation is much simpler. Asking the cpu_stop to execute
the stop_cpu() state machine on all online cpus with cpu hotplug
disabled is enough.
stop_machine itself doesn't need to manage any global resources
anymore, so all per-instance information is rolled into struct
stop_machine_data and the mutex and all static data variables are
removed.
The previous implementation created and destroyed RT workqueues as
necessary which made stop_machine() calls highly expensive on very
large machines. According to Dimitri Sivanich, preventing the dynamic
creation/destruction makes booting faster more than twice on very
large machines. cpu_stop resources are preallocated for all online
cpus and should have the same effect.
Signed-off-by: Tejun Heo <tj@kernel.org>
Acked-by: Rusty Russell <rusty@rustcorp.com.au>
Acked-by: Peter Zijlstra <peterz@infradead.org>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Dimitri Sivanich <sivanich@sgi.com>
* 'sh/for-2.6.34' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6:
sh: fix a number of Oopses and leaks in SH framebuffer driver
SH: fix error paths in DMA driver
sh: sh7751 pci controller io port fix
sh: Fix maximum number of SCIF ports in R2D defconfigs
SH: fix TS field shift calculation for DMA drivers
Current IBS code is not hotplug capable. An offline cpu might not be
initialized or deinitialized properly. This patch fixes this by
removing on_each_cpu() functions. The IBS init/deinit code is executed
in the per-cpu functions model->setup_ctrs() and model->cpu_down()
which are also called by hotplug notifiers. model->cpu_down() replaces
model->exit() that became obsolete.
Cc: Andi Kleen <andi@firstfloor.org>
Signed-off-by: Robert Richter <robert.richter@amd.com>
This patch moves the cpu notifier registration from nmi_init() to
nmi_setup(). The corresponding unregistration function is now in
nmi_shutdown(). Thus, the hotplug code is only active, if the oprofile
daemon is running.
Cc: Andi Kleen <andi@firstfloor.org>
Signed-off-by: Robert Richter <robert.richter@amd.com>
With NUMA emulation, it's possible for a single cpu to be bound
to multiple nodes since more than one may have affinity if
allocated on a physical node that is local to the cpu.
APIC ids must therefore be mapped to the lowest node ids to
maintain generic kernel use of functions such as cpu_to_node()
that determine device affinity. For example, if a device has
proximity to physical node 1, for instance, and a cpu happens to
be mapped to a higher emulated node id 8, the proximity may not
be correctly determined by comparison in generic code even
though the cpu may be truly local and allocated on physical node 1.
When this happens, the true topology of the machine isn't
accurately represented in the emulated environment; although
this isn't critical to the system's uptime, any generic code
that is NUMA aware benefits from the physical topology being
accurately represented.
This can affect any system that maps multiple APIC ids to a
single node and is booted with numa=fake=N where N is greater
than the number of physical nodes.
Signed-off-by: David Rientjes <rientjes@google.com>
Cc: Yinghai Lu <yinghai@kernel.org>
Cc: Suresh Siddha <suresh.b.siddha@intel.com>
LKML-Reference: <alpine.DEB.2.00.1005060224140.19473@chino.kir.corp.google.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
1. Remove CACHE_ALL_LOOP2 macro because it is identical to CACHE_ALL_LOOP
2. Change BUG_ON to WARN_ON
3. Remove end aligned from CACHE_LOOP_LIMITS.
C implementation do not need aligned end address and ASM code do aligned
in their macros
4. ASM optimized CACHE_RANGE_LOOP_1/2 macros needs to get aligned end address.
Because end address is compound from start + size, end address is the first address
which is exclude.
Here is the corresponding code which describe it.
+ int align = ~(line_length - 1);
+ end = ((end & align) == end) ? end - line_length : end & align;
a) end is aligned:
it is necessary to subtruct line length because we don't want to work with
next cacheline
b) end address is not aligned:
Just align it to be ready for ASM code.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Microblaze cacheline length is configurable and current cpu
uses two cacheline length 4 and 8.
We are taking conservative maximum value to be sure that cacheline
alignment is satisfied for all cases.
Here is the calculation for cacheline lenght 8 32bit=4Byte values
which is corresponding with SHIFT 5.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Based on PowerPC patche 52142e756e
PowerPC description:
On platforms doing non-coherent DMA (4xx, 8xx, ...), it's important
that the kmalloc minimum alignment is set to the cache line size, to
avoid sharing cache lines between different objects, so that DMA to
one of the objects doesn't corrupt the other.
Signed-off-by: Michal Simek <monstr@monstr.eu>
This patch fix consistent code which had problems with consistent_free
function.
I am not sure if we need to call flush_tlb_all after it but it keeps
tlbs synced.
I added noMMU and MMU version together.
Uncached shadow feature is not tested.
Signed-off-by: Michal Simek <monstr@monstr.eu>
