Enable the legacy interrupts immediately after halt interrupt is
handled, from cmdq_irq() itself.
When cmdq halt is initiated, as per existing logic driver waits either
for halt interrupt to fire or for certain period of time. In case if
cmdq is halted but halt interrupt got delayed than wait-timeout period,
driver disables cmdq interrupts since cmdq is in halt state.
The delayed halt interrupt gets fired only when cmdq is unhalted next
time and cmdq interrupts are enabled. And this delayed interrupt is
treated as an unexpected interrupt.
By enabling legacy interrupts (i.e., disabling cmdq interrupts) from
cmdq_irq(), we can ensure that we don't disable cmdq interrupts until
halt interrupt get fired. So we can avoid above mentioned scenario.
Change-Id: Ic052d41fac789b6390a5d80dfaee91767bdb783f
Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>
When system is heavily loaded, in some cases interrupt servicing
is getting effected and cmdq halt interrupt handler is getting invoked
after 1 sec delay. Since wait time of HAC interrupt in cmdq driver
is 1 sec, the delayed interrupt is being treated as unexpected
interrupt.
For fixing this case, increasing the timeout to 10 seconds.
Change-Id: I55879095aa2b81a10f40963aee02b2068a3305b4
Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>
Add ST touch controller device node for MSM8998 HDK835.
Touch controller is connected to the host processor via
I2C.
Change-Id: Id94f2feaddfa0c7aca74a52448b652afcd013ed7
Signed-off-by: Jin Fu <jinf@codeaurora.org>
In internal codec with WSA, wsa881x codec registers
accessed using soundwire expect to have delay.
So back to back registers access needs to ensure
proper delay, otherwise previous filled register
value is read and results in speaker mute.
CRs-Fixed: 2000566
Change-Id: I6b3441f206a3a9d0531b40d701636d7dd5a74cc0
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
Add address cells and size cells for digital audio node present
within analog codec node.
CRs-Fixed: 2000566
Change-Id: Iaf7ce40e9bcf8a1eabba0552377372fe2dd43ea3
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
The gcc_hmss_ahb_clk will be controlled by RPM. Remove all
control of it from the HLOS clock driver.
Change-Id: I26525787352cb0b85937cc005afba7c37a7989ff
Signed-off-by: Amit Nischal <anischal@codeaurora.org>
For SDHC version 5.0 onwards, ICE3.0 specific
registers are added in CQ register space, due to
which few CQ registers(like CQ_VENDOR_GFG,
CQ_CMD_DBG_RAM) are shifted. This change is to
update CQ register offset for sdm660.
Change-Id: Ie85b8f6c68511dccd2b545bd9cc17c747f3da8e7
Signed-off-by: Sayali Lokhande <sayalil@codeaurora.org>
