During the GDSC enable sequence, the GDS_HW_CTRL forces some
clocks to be on to trigger the handshake to unhalt the SMMU
and NOC. Once the handshake completes, the controller asserts
the PWR_ON status and disables the clocks.
If the clock driver tries enabling the SMMU ahb/axi clocks
immediately, there is a possibility that these clocks might
still not have gone through their disable sequence; especially
if the AXI/AHB rates are very low. If this happens, the clock
driver falsely assumes that the clocks are on and returns. Any
SMMU accesses/traffic at this point might lead to a failure since
the clock could turn off.
Change-Id: I544ca82e20e1c026d0ff1881c96edd33bf362b7d
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Sensor temperature read function traverses the
sensor list every time without using any lock. If the
list is undergoing mutation when it is traversed, it may
result in memory violation. For example, the new element
could have added to the list before updating the
next pointer due to out of order execution. This could result
in either NULL pointer dereference or unassigned memory access
violation. Using a lock every time when temperature
is read may mutually exclude it from list mutation, but it impacts
the performance. Sensor addition is an infrequent operation
when compared to sensor temperature read. So adding a lock
to protect against this infrequent operation will add overhead
and deter performance. Use of list_for_each_entry_safe() function
for traversing, won't help. Because this function can help
only if the traversal loop removes the current element, that
is pointed by this iteration.
Use RCU when traversing and updating the list to avoid locks.
RCU ensures list traversal safe addition or deletion happens
and doesn't block the frequent read operation. Replace the
list_for_each_entry_safe() function with rcu safe list
traversal function list_for_each_entry_rcu(), wherever it is
applicable.
Change-Id: I4c05fefa6906ecad408dfd4407b60bc051366f8c
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
Fix the following in qpnp-power-on driver:
- Use GENMASK for bit mask
- Remove unused module parameter
- Use nested comments properly wherever applicable
- Fix conditional block formatting and typos
- Use const qualifier for of_device_id table
Change-Id: Ib9dd9be6cafad4c7aec1c88d9828ef1ebbe2a1c3
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
New requests coming after/in parallel to shutdown are being
returned with DID_ERROR, but this causes the request to be
requeued and retried. These requests are getting pulled by
the shutdown context since the PON request is inserted at
the head of the queue and the queue is run for processing.
The queuecommand in ufs driver allows requests in the context
of shutdown as PON has to be sent to the device, but this
retried regular request also ends up getting submitted after
PON which fails and causes issues in err handling.
Fix this by not relying on the context but looking for the
target lun of the request. Allow only requests directed
towards well known device lun (where PON will be sent) and
block all other requests. Also make sure we mark the
shutdown processing first before taking the write lock so
that we can appropriately fail the regular request.
Change-Id: Iaa442e8e92310ea0761c27af8fda57ffcadadb3d
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
The IOVA allocator used by these calls supports IOVA address
zero so properly handle IOVA address zero.
Change-Id: I012452d4cf3534dfb79e6deb15b7ff74f5e3bb40
Signed-off-by: Liam Mark <lmark@codeaurora.org>
The smb138x device has been duplicated across many board level files.
Refactor the smb138x device to a separate dtsi file so it can be
included in any board level files.
Change-Id: I9520595f2a40e197ad2227a8391bed79412b19f8
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
Add the QSMMU device nodes that is used for address translations on
msmtriton.
Change-Id: Iff419eef01ce58fe540e8f3bd7c8a1553a340d28
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
This enables the assertion of CX ipeak mitigation during
MSS restart.
Change-Id: I113037aabafeacba7079d530ca859833f475f649
Signed-off-by: Gaurav Kohli <gkohli@codeaurora.org>
Clear the CX iPeak bit if it was set by MSS before crash.
MSS sets this bit if it was in Turbo state. In a situation
where all the votes were set (including MSS), It would have
resulted in CDSP throttling. But when MSS is in crashed state,
It cannot be cleared by MSS, So PIL needs to do this. It
would allow possible clearance of throttle state.
Change-Id: Ia561436a362dc5b0e1cb22c30ce9f5b8bb027a1f
Signed-off-by: Gaurav Kohli <gkohli@codeaurora.org>
Add support of PMFALCON PMIC and enable PMIC specific
workarounds in charger driver.
Change-Id: Id21fde25b9b741b9cb570ab5348959715e53e6cb
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
Charger and Fuel Gauge peripherals are on slave-id 0. Update
charger and FG device node to reflect the same.
Change-Id: I99d1e47a20fd5c3304249aa4f6c64e5967874312
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
Correct the required regulator node for Modem PIL for MSMFALCON Interposer
and also enable Modem pil.
Change-Id: I106ae84303f6a0b1de13ce564600f7788dd382b3
Signed-off-by: Gaurav Kohli <gkohli@codeaurora.org>
Add aggre2_snoc_axi_clk handle in USB3 node which is required to be
voted from USB driver before enabling USB core clock for msmfalcon.
Change-Id: I190233c1fc483f3d519e09784ed19e6c09ccb2bd
Signed-off-by: Vijayavardhan Vennapusa <vvreddy@codeaurora.org>
It is required to put/get vote for aggre2_snoc_axi_clk before turning
ON USB core clock for read/write transactions to be successful over
NOC from USB->DDR. Hence add support for voting aggre2_snoc_axi_clk
before enabling USB core clock as part of exiting low power mode.
Change-Id: Icb17d65fbbe49d93971905948c3dc9ab17de152a
Signed-off-by: Vijayavardhan Vennapusa <vvreddy@codeaurora.org>
Add initial version of msmfalcon GPU properties.
This is needed to support Graphics driver functionality
on msmfalcon target.
Change-Id: I7b0ccdc9a4aafef8f91ae8194f5f89838b5acbee
Signed-off-by: Rajesh Kemisetti <rajeshk@codeaurora.org>
Correct the required regulator node for Slpi PIL and also enable Slpi
PIL.
Change-Id: Ia9cb83e7f7f5c74737ddf6f6987b5acfae11e224
Signed-off-by: Gaurav Kohli <gkohli@codeaurora.org>
Correct the required regulator node for Lpass pil for MSMFALCON Interposer
and also enable Lpass pil.
Change-Id: I69d8cdddf847c3f327b03884eba7c976349ac08c
Signed-off-by: Gaurav Kohli <gkohli@codeaurora.org>
Change ufs regulators for msmfalcon interposer QRD. Reduce
maximum power load that can be drawn from vcc and vccq2 supply.
Add the required minimum and maximum voltages of ufs phy.
CRs-Fixed: 1093028
Change-Id: Ic534c518116c18e98bd4e421365831400ef967f4
Signed-off-by: xiaonian <xiaonian@codeaurora.org>
Disable CONFIG_CRYPTO_DEV_QCE flag from defconfig,
which is not required for msmfalcon.
Change-Id: I29cf58d7069d758239c2f5712e70e94be20a42d3
Signed-off-by: Brahmaji K <bkomma@codeaurora.org>
Add qrng device node with all the necessary parameters,
to enable the qrng driver on msmfalcon.
Change-Id: Ibf1eb081e58e8bf653f68cbcdfb894b6d8dab167
Signed-off-by: Brahmaji K <bkomma@codeaurora.org>
Add tz-log device node with all the necessary parameters,
to enable the TZ log driver on msmfalcon.
Change-Id: I83b13e60c46ed7565fe202a2d1ba8d2b8c06bdcc
Signed-off-by: Brahmaji K <bkomma@codeaurora.org>
Add qcrypto and qcedev device nodes with all the necessary
parameters, to enable crypto drivers on msmfalcon.
Change-Id: I9d9d4eeeb5ee41ff8a61676b19bb01b9280ae7ca
Signed-off-by: Brahmaji K <bkomma@codeaurora.org>
Add a device definition for the CPU Error Reporting
hardware on msmtriton, to allow hardware errors to be
reported to software.
Change-Id: I36561c446ade0ee36dfb266c6033ae7734af4df9
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
Add a device definition for the CPU Error Reporting
hardware on msmfalcon, to allow hardware errors to be
reported to software.
Change-Id: I73c3a129bd206e4c1c275a55f550e1ce847985c0
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
Add cpu cache nodes to represent the cache hierarchy and
to specify the dump size of each cache.
While at it also add the cache dump nodes which will enable
reserving the memory for cache dumps.
Change-Id: I1d80ac853eb283c411985ceebd0dc31ed046836a
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
Reg updates can only miss on PIX stream since reg updates
are forced for RDI streams. This also prevents the error
check from being called multiple times for PIX streams.
CRs-Fixed: 1089937
Change-Id: Ibe0ea7efabc5a8452f05fdc2ab8b3ec7931a66e7
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
Stats buffer done was not coming after device reset because the
sequence for turning on stats was not right. Follow the same
sequence which is followed on start stream for stats during
recovery. Also, for vfe 46 version fix the write master offset.
CRs-Fixed: 1089758
Change-Id: I47849097022817dc411c31e3aadf037f6cae9a72
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
If user requests the camif to be stopped immediately then do so.
Only user driver will know if input has already streamed off in
which case camif shopuld be stopped immediately as per the
user driver request.
CRs-Fixed: 1089754
Change-Id: I47df74cb72e41b3c00fcebaab9d709818820ed47
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
If buffer is not available during stream start then do not treat
that as an error.
CRs-Fixed: 1087368
Change-Id: I8f56bbf621313676282e06449431d1961d4819eb
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
