93466ced5d
Change support for 32bit app specific settings. The change made earlier was not correct for 8996pro devices so correct it to include all variants of 8996. Change-Id: Id6afad04ad316dd7a41743821b7cfd513db227e5 Signed-off-by: Imran Khan <kimran@codeaurora.org> Signed-off-by: Zhiqiang Tu <ztu@codeaurora.org>
135 lines
3.5 KiB
C
135 lines
3.5 KiB
C
/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/bitops.h>
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#include <linux/spinlock.h>
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#include <linux/cpu.h>
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#include <linux/export.h>
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#include <asm/app_api.h>
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static spinlock_t spinlock;
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static spinlock_t spinlock_32bit_app;
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static DEFINE_PER_CPU(int, app_config_applied);
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static unsigned long app_config_set[NR_CPUS];
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static unsigned long app_config_clear[NR_CPUS];
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void set_app_setting_bit(uint32_t bit)
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{
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unsigned long flags;
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uint64_t reg;
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int cpu;
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spin_lock_irqsave(&spinlock, flags);
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asm volatile("mrs %0, S3_1_C15_C15_0" : "=r" (reg));
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reg = reg | BIT(bit);
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isb();
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asm volatile("msr S3_1_C15_C15_0, %0" : : "r" (reg));
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isb();
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if (bit == APP_SETTING_BIT) {
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cpu = raw_smp_processor_id();
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app_config_set[cpu]++;
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this_cpu_write(app_config_applied, 1);
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}
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spin_unlock_irqrestore(&spinlock, flags);
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}
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EXPORT_SYMBOL(set_app_setting_bit);
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void clear_app_setting_bit(uint32_t bit)
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{
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unsigned long flags;
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uint64_t reg;
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int cpu;
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spin_lock_irqsave(&spinlock, flags);
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asm volatile("mrs %0, S3_1_C15_C15_0" : "=r" (reg));
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reg = reg & ~BIT(bit);
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isb();
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asm volatile("msr S3_1_C15_C15_0, %0" : : "r" (reg));
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isb();
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if (bit == APP_SETTING_BIT) {
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cpu = raw_smp_processor_id();
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app_config_clear[cpu]++;
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this_cpu_write(app_config_applied, 0);
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}
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spin_unlock_irqrestore(&spinlock, flags);
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}
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EXPORT_SYMBOL(clear_app_setting_bit);
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void set_app_setting_bit_for_32bit_apps(void)
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{
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unsigned long flags;
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uint64_t reg;
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spin_lock_irqsave(&spinlock_32bit_app, flags);
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if (use_32bit_app_setting) {
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asm volatile("mrs %0, S3_0_c15_c15_0 " : "=r" (reg));
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reg = reg | BIT(24);
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isb();
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asm volatile("msr S3_0_c15_c15_0, %0" : : "r" (reg));
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isb();
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asm volatile("mrs %0, S3_0_c15_c15_1 " : "=r" (reg));
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reg = reg | BIT(18) | BIT(2) | BIT(0);
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isb();
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asm volatile("msr S3_0_c15_c15_1, %0" : : "r" (reg));
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isb();
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} else if (use_32bit_app_setting_pro) {
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asm volatile("mrs %0, S3_0_c15_c15_1 " : "=r" (reg));
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reg = reg | BIT(18);
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isb();
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asm volatile("msr S3_0_c15_c15_1, %0" : : "r" (reg));
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isb();
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}
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spin_unlock_irqrestore(&spinlock_32bit_app, flags);
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}
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EXPORT_SYMBOL(set_app_setting_bit_for_32bit_apps);
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void clear_app_setting_bit_for_32bit_apps(void)
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{
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unsigned long flags;
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uint64_t reg;
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spin_lock_irqsave(&spinlock_32bit_app, flags);
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if (use_32bit_app_setting) {
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asm volatile("mrs %0, S3_0_c15_c15_0 " : "=r" (reg));
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reg = reg & ~BIT(24);
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isb();
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asm volatile("msr S3_0_c15_c15_0, %0" : : "r" (reg));
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isb();
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asm volatile("mrs %0, S3_0_c15_c15_1 " : "=r" (reg));
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reg = reg & ~BIT(18);
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reg = reg & ~BIT(2);
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reg = reg & ~BIT(0);
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isb();
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asm volatile("msr S3_0_c15_c15_1, %0" : : "r" (reg));
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isb();
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} else if (use_32bit_app_setting_pro) {
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asm volatile("mrs %0, S3_0_c15_c15_1 " : "=r" (reg));
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reg = reg & ~BIT(18);
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isb();
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asm volatile("msr S3_0_c15_c15_1, %0" : : "r" (reg));
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isb();
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}
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spin_unlock_irqrestore(&spinlock_32bit_app, flags);
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}
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EXPORT_SYMBOL(clear_app_setting_bit_for_32bit_apps);
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static int __init init_app_api(void)
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{
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spin_lock_init(&spinlock);
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spin_lock_init(&spinlock_32bit_app);
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return 0;
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}
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early_initcall(init_app_api);
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