Exact

Exact Union RegExp

Chen Zhong 22a1e337ed clk: mediatek: add the option for determining PLL source clock ... [ Upstream commit c955bf3998efa3355790a4d8c82874582f1bc727 ] Since the previous setup always sets the PLL using crystal 26MHz, this doesn't always happen in every MediaTek platform. So the patch added flexibility for assigning extra member for determining the PLL source clock. Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Sasha Levin <alexander.levin@verizon.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2017-12-20 10:04:59 +01:00
..
clk-apmixed.c
clk-gate.c
clk-gate.h
clk-mt8135.c
clk-mt8173.c
clk-mtk.c
clk-mtk.h	clk: mediatek: add the option for determining PLL source clock	2017-12-20 10:04:59 +01:00
clk-pll.c	clk: mediatek: add the option for determining PLL source clock	2017-12-20 10:04:59 +01:00
Makefile
reset.c