Due to an egregious misunderstanding of the specification it was thought that to do the TTBR1 matching correctly the sign extension bit needed to match the input address space. This is incorrect - the TTBR1 range is determined by the size of the TTBR1 space (in our case, the same as the input address space). For example if the input address size is 36, the effective range of the pagetables are: TTBR0: 0x00000000_00000000 - 0x0000000f_ffffffff TTBR1: 0xfffffff0_00000000 - 0xffffffff_ffffffff For its part the sign extension bit needs should be set based on the upstream bus size. If the device has a UBS of 49 then the sign extension bit is assumed by design to be 48 otherwise the driver needs to pick the highest available bit and reduce the input address space by 1. Because the client driver shouldn't need to know the upstream bus size, convention is to use a fully sign extended unsigned long address for TTBR1 mappings. If the sign extension bit is set lower than the upstream bus size some implementations assume that bits above the sign extension bit need to be zero and breaks the convention. Setting the sign extension bit correctly for the upstream bus size ensures that sign extension always works. The hardware will match an address to the TTBR1 if all the bits between the sign extension bit and the input address size are set to 1. We emulate this behavior in software when looking up a pagetable for a software operation. Change-Id: Ic0dedbad80c72f11bc8a7e6792f0e3c2f58bc674 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
216 lines
6.8 KiB
C
216 lines
6.8 KiB
C
#ifndef __IO_PGTABLE_H
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#define __IO_PGTABLE_H
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#include <linux/scatterlist.h>
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#include <soc/qcom/msm_tz_smmu.h>
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/*
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* Public API for use by IOMMU drivers
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*/
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enum io_pgtable_fmt {
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ARM_32_LPAE_S1,
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ARM_32_LPAE_S2,
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ARM_64_LPAE_S1,
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ARM_64_LPAE_S2,
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ARM_MSM_SECURE,
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ARM_V8L_FAST,
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IO_PGTABLE_NUM_FMTS,
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};
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/**
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* struct iommu_gather_ops - IOMMU callbacks for TLB and page table management.
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*
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* @tlb_flush_all: Synchronously invalidate the entire TLB context.
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* @tlb_add_flush: Queue up a TLB invalidation for a virtual address range.
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* @tlb_sync: Ensure any queued TLB invalidation has taken effect, and
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* any corresponding page table updates are visible to the
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* IOMMU.
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* @alloc_pages_exact: Allocate page table memory (optional, defaults to
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* alloc_pages_exact)
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* @free_pages_exact: Free page table memory (optional, defaults to
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* free_pages_exact)
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*
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* Note that these can all be called in atomic context and must therefore
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* not block.
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*/
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struct iommu_gather_ops {
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void (*tlb_flush_all)(void *cookie);
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void (*tlb_add_flush)(unsigned long iova, size_t size, bool leaf,
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void *cookie);
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void (*tlb_sync)(void *cookie);
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void *(*alloc_pages_exact)(void *cookie, size_t size, gfp_t gfp_mask);
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void (*free_pages_exact)(void *cookie, void *virt, size_t size);
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};
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/**
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* struct io_pgtable_cfg - Configuration data for a set of page tables.
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*
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* @quirks: A bitmap of hardware quirks that require some special
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* action by the low-level page table allocator.
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* @pgsize_bitmap: A bitmap of page sizes supported by this set of page
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* tables.
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* @ias: Input address (iova) size, in bits.
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* @oas: Output address (paddr) size, in bits.
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* @tlb: TLB management callbacks for this set of tables.
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* @iommu_dev: The device representing the DMA configuration for the
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* page table walker.
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*/
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struct io_pgtable_cfg {
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/*
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* IO_PGTABLE_QUIRK_PAGE_TABLE_COHERENT: Set the page table as
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* coherent.
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*/
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#define IO_PGTABLE_QUIRK_ARM_NS (1 << 0) /* Set NS bit in PTEs */
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#define IO_PGTABLE_QUIRK_PAGE_TABLE_COHERENT (1 << 1)
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#define IO_PGTABLE_QUIRK_ARM_TTBR1 (1 << 2) /* Allocate TTBR1 PT */
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int quirks;
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unsigned long pgsize_bitmap;
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unsigned int ias;
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unsigned int oas;
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int sep;
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const struct iommu_gather_ops *tlb;
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struct device *iommu_dev;
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dma_addr_t iova_base;
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dma_addr_t iova_end;
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/* Low-level data specific to the table format */
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union {
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struct {
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u64 ttbr[2];
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u64 tcr;
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u64 mair[2];
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} arm_lpae_s1_cfg;
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struct {
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u64 vttbr;
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u64 vtcr;
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} arm_lpae_s2_cfg;
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struct {
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enum tz_smmu_device_id sec_id;
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int cbndx;
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} arm_msm_secure_cfg;
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struct {
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u64 ttbr[2];
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u64 tcr;
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u64 mair[2];
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void *pmds;
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} av8l_fast_cfg;
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};
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};
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/**
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* struct io_pgtable_ops - Page table manipulation API for IOMMU drivers.
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*
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* @map: Map a physically contiguous memory region.
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* @map_sg: Map a scatterlist. Returns the number of bytes mapped,
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* or 0 on failure. The size parameter contains the size
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* of the partial mapping in case of failure.
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* @unmap: Unmap a physically contiguous memory region.
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* @iova_to_phys: Translate iova to physical address.
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*
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* These functions map directly onto the iommu_ops member functions with
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* the same names.
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*/
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struct io_pgtable_ops {
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int (*map)(struct io_pgtable_ops *ops, unsigned long iova,
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phys_addr_t paddr, size_t size, int prot);
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int (*map_sg)(struct io_pgtable_ops *ops, unsigned long iova,
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struct scatterlist *sg, unsigned int nents,
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int prot, size_t *size);
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size_t (*unmap)(struct io_pgtable_ops *ops, unsigned long iova,
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size_t size);
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phys_addr_t (*iova_to_phys)(struct io_pgtable_ops *ops,
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unsigned long iova);
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bool (*is_iova_coherent)(struct io_pgtable_ops *ops,
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unsigned long iova);
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uint64_t (*iova_to_pte)(struct io_pgtable_ops *ops,
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unsigned long iova);
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};
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/**
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* alloc_io_pgtable_ops() - Allocate a page table allocator for use by an IOMMU.
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*
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* @fmt: The page table format.
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* @cfg: The page table configuration. This will be modified to represent
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* the configuration actually provided by the allocator (e.g. the
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* pgsize_bitmap may be restricted).
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* @cookie: An opaque token provided by the IOMMU driver and passed back to
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* the callback routines in cfg->tlb.
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*/
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struct io_pgtable_ops *alloc_io_pgtable_ops(enum io_pgtable_fmt fmt,
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struct io_pgtable_cfg *cfg,
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void *cookie);
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/**
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* free_io_pgtable_ops() - Free an io_pgtable_ops structure. The caller
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* *must* ensure that the page table is no longer
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* live, but the TLB can be dirty.
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*
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* @ops: The ops returned from alloc_io_pgtable_ops.
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*/
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void free_io_pgtable_ops(struct io_pgtable_ops *ops);
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/*
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* Internal structures for page table allocator implementations.
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*/
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/**
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* struct io_pgtable - Internal structure describing a set of page tables.
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*
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* @fmt: The page table format.
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* @cookie: An opaque token provided by the IOMMU driver and passed back to
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* any callback routines.
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* @cfg: A copy of the page table configuration.
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* @ops: The page table operations in use for this set of page tables.
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*/
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struct io_pgtable {
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enum io_pgtable_fmt fmt;
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void *cookie;
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struct io_pgtable_cfg cfg;
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struct io_pgtable_ops ops;
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};
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/**
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* struct io_pgtable_init_fns - Alloc/free a set of page tables for a
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* particular format.
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*
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* @alloc: Allocate a set of page tables described by cfg.
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* @free: Free the page tables associated with iop.
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*/
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struct io_pgtable_init_fns {
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struct io_pgtable *(*alloc)(struct io_pgtable_cfg *cfg, void *cookie);
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void (*free)(struct io_pgtable *iop);
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};
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/**
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* io_pgtable_alloc_pages_exact - allocate an exact number physically-contiguous pages.
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* @size: the number of bytes to allocate
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* @gfp_mask: GFP flags for the allocation
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*
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* Like alloc_pages_exact(), but with some additional accounting for debug
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* purposes.
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*/
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void *io_pgtable_alloc_pages_exact(struct io_pgtable_cfg *cfg, void *cookie,
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size_t size, gfp_t gfp_mask);
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/**
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* io_pgtable_free_pages_exact - release memory allocated via io_pgtable_alloc_pages_exact()
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* @virt: the value returned by alloc_pages_exact.
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* @size: size of allocation, same value as passed to alloc_pages_exact().
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*
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* Like free_pages_exact(), but with some additional accounting for debug
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* purposes.
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*/
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void io_pgtable_free_pages_exact(struct io_pgtable_cfg *cfg, void *cookie,
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void *virt, size_t size);
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extern struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s1_init_fns;
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extern struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s2_init_fns;
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extern struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s1_init_fns;
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extern struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s2_init_fns;
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#endif /* __IO_PGTABLE_H */
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