ca585cf9fb
Adds basic platform devices for Loongson 1B, including serial port, ethernet, USB, RTC and interrupt handler. The Loongson 1B UART is compatible with NS16550A, the Loongson 1B GMAC is built around a Synopsys IP Core. Use normal instead of enhanced descriptors. Thanks to Giuseppe for updating the normal descriptor in stmmac driver. Thanks to Zhao Zhang for implementing the RTC driver. Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: wuzhangjin@gmail.com Cc: zhzhl555@gmail.com Cc: Kelvin Cheung <keguang.zhang@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/4133/ Patchwork: https://patchwork.linux-mips.org/patch/4134/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
25 lines
803 B
C
25 lines
803 B
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
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*/
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#ifndef __ASM_MACH_LOONGSON1_WAR_H
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#define __ASM_MACH_LOONGSON1_WAR_H
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#define R4600_V1_INDEX_ICACHEOP_WAR 0
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#define R4600_V1_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define R5432_CP0_INTERRUPT_WAR 0
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#define MIPS4K_ICACHE_REFILL_WAR 0
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#define MIPS_CACHE_SYNC_WAR 0
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#define TX49XX_ICACHE_INDEX_INV_WAR 0
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#define RM9000_CDEX_SMP_WAR 0
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#define ICACHE_REFILLS_WORKAROUND_WAR 0
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#define R10000_LLSC_WAR 0
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#define MIPS34K_MISSED_ITLB_WAR 0
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#endif /* __ASM_MACH_LOONGSON1_WAR_H */
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