0bb34a6bf1
This consolidates the pci_iomap() definitions and reworks how the I/O port base is handled. PCI channels can register their own I/O map base, or if none is provided, the system-wide generic I/O base is used instead. Functionally nothing changes, while this allows us to kill off lots of I/O address special casing and lookups. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
119 lines
3.2 KiB
C
119 lines
3.2 KiB
C
#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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unsigned long PCIBIOS_MIN_IO = 0x0000;
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unsigned long PCIBIOS_MIN_MEM = 0;
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/*
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* We need to avoid collisions with `mirrored' VGA ports
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* and other strange ISA hardware, so we always want the
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* addresses to be allocated in the 0x000-0x0ff region
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* modulo 0x400.
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*/
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void pcibios_align_resource(void *data, struct resource *res,
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resource_size_t size, resource_size_t align)
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{
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struct pci_dev *dev = data;
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struct pci_channel *chan = dev->sysdata;
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resource_size_t start = res->start;
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if (res->flags & IORESOURCE_IO) {
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if (start < PCIBIOS_MIN_IO + chan->io_resource->start)
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start = PCIBIOS_MIN_IO + chan->io_resource->start;
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/*
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* Put everything into 0x00-0xff region modulo 0x400.
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*/
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if (start & 0x300) {
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start = (start + 0x3ff) & ~0x3ff;
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res->start = start;
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}
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} else if (res->flags & IORESOURCE_MEM) {
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if (start < PCIBIOS_MIN_MEM + chan->mem_resource->start)
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start = PCIBIOS_MIN_MEM + chan->mem_resource->start;
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}
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res->start = start;
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}
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int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
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enum pci_mmap_state mmap_state, int write_combine)
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{
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/*
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* I/O space can be accessed via normal processor loads and stores on
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* this platform but for now we elect not to do this and portable
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* drivers should not do this anyway.
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*/
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if (mmap_state == pci_mmap_io)
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return -EINVAL;
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/*
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* Ignore write-combine; for now only return uncached mappings.
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*/
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vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
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return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
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vma->vm_end - vma->vm_start,
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vma->vm_page_prot);
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}
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static void __iomem *ioport_map_pci(struct pci_dev *dev,
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unsigned long port, unsigned int nr)
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{
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struct pci_channel *chan = dev->sysdata;
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if (!chan->io_map_base)
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chan->io_map_base = generic_io_base;
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return (void __iomem *)(chan->io_map_base + port);
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}
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void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
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{
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resource_size_t start = pci_resource_start(dev, bar);
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resource_size_t len = pci_resource_len(dev, bar);
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unsigned long flags = pci_resource_flags(dev, bar);
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if (unlikely(!len || !start))
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return NULL;
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if (maxlen && len > maxlen)
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len = maxlen;
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if (flags & IORESOURCE_IO)
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return ioport_map_pci(dev, start, len);
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/*
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* Presently the IORESOURCE_MEM case is a bit special, most
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* SH7751 style PCI controllers have PCI memory at a fixed
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* location in the address space where no remapping is desired.
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* With the IORESOURCE_MEM case more care has to be taken
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* to inhibit page table mapping for legacy cores, but this is
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* punted off to __ioremap().
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* -- PFM.
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*/
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if (flags & IORESOURCE_MEM) {
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if (flags & IORESOURCE_CACHEABLE)
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return ioremap(start, len);
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return ioremap_nocache(start, len);
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}
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return NULL;
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}
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EXPORT_SYMBOL(pci_iomap);
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void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
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{
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iounmap(addr);
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}
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EXPORT_SYMBOL(pci_iounmap);
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#ifdef CONFIG_HOTPLUG
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EXPORT_SYMBOL(pcibios_resource_to_bus);
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EXPORT_SYMBOL(pcibios_bus_to_resource);
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EXPORT_SYMBOL(PCIBIOS_MIN_IO);
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EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
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#endif
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