4580104222
Without the isbs in arch_timer_get_cnt{p,v}ct the cpu may speculate
reads and return stale values. This could be bad for code sensitive to
changes in expected deltas between calls (e.g. the delay loop).
Without isbs in arch_timer_reg_write the processor may reorder
instructions around enabling/disabling of the timer or writing the
compare value, which we probably don't want.
This patch adds isbs to prevent those issues.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
126 lines
2.6 KiB
C
126 lines
2.6 KiB
C
#ifndef __ASMARM_ARCH_TIMER_H
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#define __ASMARM_ARCH_TIMER_H
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#include <asm/barrier.h>
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#include <asm/errno.h>
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#include <linux/clocksource.h>
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#include <linux/types.h>
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#ifdef CONFIG_ARM_ARCH_TIMER
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int arch_timer_of_register(void);
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int arch_timer_sched_clock_init(void);
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struct timecounter *arch_timer_get_timecounter(void);
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#define ARCH_TIMER_CTRL_ENABLE (1 << 0)
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#define ARCH_TIMER_CTRL_IT_MASK (1 << 1)
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#define ARCH_TIMER_CTRL_IT_STAT (1 << 2)
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#define ARCH_TIMER_REG_CTRL 0
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#define ARCH_TIMER_REG_TVAL 1
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#define ARCH_TIMER_PHYS_ACCESS 0
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#define ARCH_TIMER_VIRT_ACCESS 1
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/*
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* These register accessors are marked inline so the compiler can
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* nicely work out which register we want, and chuck away the rest of
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* the code. At least it does so with a recent GCC (4.6.3).
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*/
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static inline void arch_timer_reg_write(const int access, const int reg, u32 val)
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{
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if (access == ARCH_TIMER_PHYS_ACCESS) {
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
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break;
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case ARCH_TIMER_REG_TVAL:
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asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val));
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break;
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}
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}
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if (access == ARCH_TIMER_VIRT_ACCESS) {
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" (val));
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break;
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case ARCH_TIMER_REG_TVAL:
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asm volatile("mcr p15, 0, %0, c14, c3, 0" : : "r" (val));
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break;
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}
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}
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isb();
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}
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static inline u32 arch_timer_reg_read(const int access, const int reg)
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{
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u32 val = 0;
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if (access == ARCH_TIMER_PHYS_ACCESS) {
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
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break;
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case ARCH_TIMER_REG_TVAL:
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asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
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break;
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}
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}
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if (access == ARCH_TIMER_VIRT_ACCESS) {
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val));
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break;
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case ARCH_TIMER_REG_TVAL:
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asm volatile("mrc p15, 0, %0, c14, c3, 0" : "=r" (val));
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break;
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}
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}
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return val;
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}
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static inline u32 arch_timer_get_cntfrq(void)
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{
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u32 val;
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asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
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return val;
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}
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static inline u64 arch_counter_get_cntpct(void)
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{
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u64 cval;
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isb();
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asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval));
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return cval;
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}
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static inline u64 arch_counter_get_cntvct(void)
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{
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u64 cval;
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isb();
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asm volatile("mrrc p15, 1, %Q0, %R0, c14" : "=r" (cval));
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return cval;
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}
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#else
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static inline int arch_timer_of_register(void)
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{
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return -ENXIO;
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}
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static inline int arch_timer_sched_clock_init(void)
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{
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return -ENXIO;
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}
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static inline struct timecounter *arch_timer_get_timecounter(void)
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{
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return NULL;
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}
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#endif
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#endif
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