d3c08a3ced
Enable update xfer for DBM while configuring dbm endpoint and also clear update xfer before queueing end xfer command as part of endpoint disable as hardware programming guide. CRs-Fixed: 965207 Change-Id: Ib5ec650884ad06394280416ccf877c1ccce1eaaf Signed-off-by: Vijayavardhan Vennapusa <vvreddy@codeaurora.org> Signed-off-by: Chandana Kishori Chiluveru <cchiluve@codeaurora.org>
75 lines
2.3 KiB
C
75 lines
2.3 KiB
C
/* Copyright (c) 2012-2016, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __DBM_H
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#define __DBM_H
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#include <linux/device.h>
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#include <linux/types.h>
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/**
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* USB DBM Hardware registers bitmask.
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*
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*/
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/* DBM_EP_CFG */
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#define DBM_EN_EP 0x00000001
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#define USB3_EPNUM 0x0000003E
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#define DBM_BAM_PIPE_NUM 0x000000C0
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#define DBM_PRODUCER 0x00000100
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#define DBM_DISABLE_WB 0x00000200
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#define DBM_INT_RAM_ACC 0x00000400
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/* DBM_DATA_FIFO_SIZE */
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#define DBM_DATA_FIFO_SIZE_MASK 0x0000ffff
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/* DBM_GEVNTSIZ */
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#define DBM_GEVNTSIZ_MASK 0x0000ffff
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/* DBM_DBG_CNFG */
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#define DBM_ENABLE_IOC_MASK 0x0000000f
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/* DBM_SOFT_RESET */
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#define DBM_SFT_RST_EP0 0x00000001
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#define DBM_SFT_RST_EP1 0x00000002
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#define DBM_SFT_RST_EP2 0x00000004
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#define DBM_SFT_RST_EP3 0x00000008
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#define DBM_SFT_RST_EPS_MASK 0x0000000F
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#define DBM_SFT_RST_MASK 0x80000000
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#define DBM_EN_MASK 0x00000002
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/* DBM TRB configurations */
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#define DBM_TRB_BIT 0x80000000
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#define DBM_TRB_DATA_SRC 0x40000000
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#define DBM_TRB_DMA 0x20000000
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#define DBM_TRB_EP_NUM(ep) (ep<<24)
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struct dbm;
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struct dbm *usb_get_dbm_by_phandle(struct device *dev, const char *phandle);
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int dbm_soft_reset(struct dbm *dbm, bool enter_reset);
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int dbm_ep_config(struct dbm *dbm, u8 usb_ep, u8 bam_pipe, bool producer,
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bool disable_wb, bool internal_mem, bool ioc);
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int dbm_ep_unconfig(struct dbm *dbm, u8 usb_ep);
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int dbm_get_num_of_eps_configured(struct dbm *dbm);
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int dbm_event_buffer_config(struct dbm *dbm, u32 addr_lo, u32 addr_hi,
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int size);
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int dwc3_dbm_disable_update_xfer(struct dbm *dbm, u8 usb_ep);
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int dbm_data_fifo_config(struct dbm *dbm, u8 dep_num, phys_addr_t addr,
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u32 size, u8 dst_pipe_idx);
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void dbm_set_speed(struct dbm *dbm, bool speed);
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void dbm_enable(struct dbm *dbm);
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int dbm_ep_soft_reset(struct dbm *dbm, u8 usb_ep, bool enter_reset);
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bool dbm_reset_ep_after_lpm(struct dbm *dbm);
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bool dbm_l1_lpm_interrupt(struct dbm *dbm);
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#endif /* __DBM_H */
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