Dmitry Osipenko 12060f4740 clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides divider ... commit 40db569d6769ffa3864fd1b89616b1a7323568a8 upstream. There are wrongly set parenthesis in the code that are resulting in a wrong configuration being programmed for PLLM. The original fix was made by Danny Huang in the downstream kernel. The patch was tested on Nyan Big Tegra124 chromebook, PLLM rate changing works correctly now and system doesn't lock up after changing the PLLM rate due to EMC scaling. Cc: <stable@vger.kernel.org> Tested-by: Steev Klimaszewski <steev@kali.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2019-06-11 12:23:45 +02:00
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at91	clk: at91: fix check of clk_register() returned value	2016-06-07 18:14:34 -07:00
bcm	clk: bcm2835: De-assert/assert PLL reset signal when appropriate	2018-04-24 09:32:08 +02:00
berlin
h8300
hisilicon
imx	clk: imx6sl: ensure MMDC CH0 handshake is bypassed	2019-02-20 10:13:08 +01:00
ingenic	clk: ingenic: Fix round_rate misbehaving with non-integer dividers	2019-03-23 08:44:36 +01:00
keystone
mediatek	clk: mediatek: add the option for determining PLL source clock	2017-12-20 10:04:59 +01:00
meson	clk: meson: Fix meson_clk_register_clks() signature type mismatch	2016-05-11 11:21:12 +02:00
mmp	clk: mmp: Off by one in mmp_clk_add()	2018-12-21 14:09:53 +01:00
mvebu	clk: mvebu: armada-38x: add support for missing clocks	2018-04-24 09:32:08 +02:00
mxs
nxp	clk-divider: make sure read-only dividers do not write to their register	2016-05-11 11:21:11 +02:00
pistachio
pxa
qcom	clk: qcom: msm8916: fix mnd_width for codec_digcodec	2018-03-22 09:23:28 +01:00
rockchip	clk: rockchip: Prevent calculating mmc phase if clock rate is zero	2018-05-30 07:49:14 +02:00
samsung	clk: samsung: exynos5420: Enable PERIS clocks for suspend	2018-11-27 16:08:00 +01:00
shmobile
sirf
socfpga
spear
st
sunxi	clk: sunxi: Add apb0 gates for H3	2017-05-02 21:19:47 -07:00
tegra	clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides divider	2019-06-11 12:23:45 +02:00
ti	clk: ti: dra7-atl-clock: fix child-node lookups	2017-11-30 08:37:23 +00:00
ux500
versatile	clk: versatile: sp810: support reentrance	2016-05-11 11:21:12 +02:00
x86
zte
zynq
clk-asm9260.c
clk-axi-clkgen.c
clk-axm5516.c
clk-cdce706.c
clk-cdce925.c
clk-clps711x.c
clk-composite.c
clk-conf.c	clk: Fix __set_clk_rates error print-string	2018-04-13 19:50:16 +02:00
clk-devres.c
clk-divider.c	clk: divider: Fix clk_divider_round_rate() to use clk_readl()	2016-10-31 04:14:01 -06:00
clk-efm32gg.c
clk-fixed-factor.c
clk-fixed-rate.c
clk-fractional-divider.c
clk-gate.c
clk-gpio.c
clk-highbank.c
clk-ls1x.c
clk-max-gen.c
clk-max-gen.h
clk-max77686.c
clk-max77802.c
clk-mb86s7x.c
clk-moxart.c
clk-multiplier.c
clk-mux.c
clk-nomadik.c
clk-nspire.c
clk-palmas.c
clk-pwm.c
clk-qoriq.c	clk: qoriq: Don't allow CPU clocks higher than starting value	2016-11-18 10:48:35 +01:00
clk-rk808.c
clk-s2mps11.c	clk: s2mps11: Fix matching when built as module and DT node contains compatible	2018-11-21 09:27:41 +01:00
clk-scpi.c	clk: scpi: fix return type of __scpi_dvfs_round_rate	2018-04-13 19:50:16 +02:00
clk-si514.c
clk-si570.c
clk-si5351.c	clk: si5351: Rename internal plls to avoid name collisions	2018-03-24 10:58:48 +01:00
clk-si5351.h
clk-stm32f4.c
clk-twl6040.c
clk-u300.c
clk-vt8500.c
clk-wm831x.c	clk: clk-wm831x: fix a logic error	2017-01-12 11:22:48 +01:00
clk-xgene.c	clk: xgene: Add missing parenthesis when clearing divider value	2016-10-07 15:23:47 +02:00
clk.c	clk: Don't show the incorrect clock phase	2018-05-30 07:49:11 +02:00
clk.h
clkdev.c
Kconfig
Makefile	clk: Make x86/ conditional on CONFIG_COMMON_CLK	2017-05-14 13:32:55 +02:00