d98585de72
ICE init & reset can be synchronous now because ICE does not need to go to secure side for any ICE configuration. This would simplify interface and make call more efficient. Change-Id: I7aa4e2d3ba3383d25758b21b8ae261a0220f35f9 Signed-off-by: Dinesh K Garg <dineshg@codeaurora.org> Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org> Signed-off-by: Gilad Broner <gbroner@codeaurora.org> [subhashj@codeaurora.org: fixed merge conflicts, dropped changes to ICE and UFS driver as they are already present] Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
138 lines
3.8 KiB
C
138 lines
3.8 KiB
C
/*
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __SDHCI_MSM_ICE_H__
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#define __SDHCI_MSM_ICE_H__
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/blkdev.h>
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#include <crypto/ice.h>
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#include "sdhci-msm.h"
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#define SDHC_MSM_CRYPTO_LABEL "sdhc-msm-crypto"
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/* Timeout waiting for ICE initialization, that requires TZ access */
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#define SDHCI_MSM_ICE_COMPLETION_TIMEOUT_MS 500
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/*
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* SDHCI host controller ICE registers. There are n [0..31]
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* of each of these registers
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*/
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#define NUM_SDHCI_MSM_ICE_CTRL_INFO_n_REGS 32
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#define CORE_VENDOR_SPEC_ICE_CTRL 0x300
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#define CORE_VENDOR_SPEC_ICE_CTRL_INFO_1_n 0x304
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#define CORE_VENDOR_SPEC_ICE_CTRL_INFO_2_n 0x308
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#define CORE_VENDOR_SPEC_ICE_CTRL_INFO_3_n 0x30C
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/* SDHCI MSM ICE CTRL Info register offset */
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enum {
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OFFSET_SDHCI_MSM_ICE_CTRL_INFO_BYPASS = 0,
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OFFSET_SDHCI_MSM_ICE_CTRL_INFO_KEY_INDEX = 0x1,
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OFFSET_SDHCI_MSM_ICE_CTRL_INFO_CDU = 0x6,
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};
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/* SDHCI MSM ICE CTRL Info register masks */
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enum {
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MASK_SDHCI_MSM_ICE_CTRL_INFO_BYPASS = 0x1,
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MASK_SDHCI_MSM_ICE_CTRL_INFO_KEY_INDEX = 0x1F,
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MASK_SDHCI_MSM_ICE_CTRL_INFO_CDU = 0x7,
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};
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/* SDHCI MSM ICE encryption/decryption bypass state */
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enum {
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SDHCI_MSM_ICE_DISABLE_BYPASS = 0,
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SDHCI_MSM_ICE_ENABLE_BYPASS = 1,
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};
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/* SDHCI MSM ICE Crypto Data Unit of target DUN of Transfer Request */
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enum {
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SDHCI_MSM_ICE_TR_DATA_UNIT_512_B = 0,
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SDHCI_MSM_ICE_TR_DATA_UNIT_1_KB = 1,
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SDHCI_MSM_ICE_TR_DATA_UNIT_2_KB = 2,
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SDHCI_MSM_ICE_TR_DATA_UNIT_4_KB = 3,
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SDHCI_MSM_ICE_TR_DATA_UNIT_8_KB = 4,
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SDHCI_MSM_ICE_TR_DATA_UNIT_16_KB = 5,
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SDHCI_MSM_ICE_TR_DATA_UNIT_32_KB = 6,
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SDHCI_MSM_ICE_TR_DATA_UNIT_64_KB = 7,
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};
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/* SDHCI MSM ICE internal state */
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enum {
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SDHCI_MSM_ICE_STATE_DISABLED = 0,
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SDHCI_MSM_ICE_STATE_ACTIVE = 1,
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SDHCI_MSM_ICE_STATE_SUSPENDED = 2,
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};
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#ifdef CONFIG_MMC_SDHCI_MSM_ICE
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int sdhci_msm_ice_get_dev(struct sdhci_host *host);
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int sdhci_msm_ice_init(struct sdhci_host *host);
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void sdhci_msm_ice_cfg_reset(struct sdhci_host *host, u32 slot);
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int sdhci_msm_ice_cfg(struct sdhci_host *host, struct mmc_request *mrq,
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u32 slot);
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int sdhci_msm_ice_reset(struct sdhci_host *host);
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int sdhci_msm_ice_resume(struct sdhci_host *host);
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int sdhci_msm_ice_suspend(struct sdhci_host *host);
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int sdhci_msm_ice_get_status(struct sdhci_host *host, int *ice_status);
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void sdhci_msm_ice_print_regs(struct sdhci_host *host);
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#else
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inline int sdhci_msm_ice_get_dev(struct sdhci_host *host)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_msm_host *msm_host = pltfm_host->priv;
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if (msm_host) {
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msm_host->ice.pdev = NULL;
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msm_host->ice.vops = NULL;
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}
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return -ENODEV;
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}
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inline int sdhci_msm_ice_init(struct sdhci_host *host)
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{
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return 0;
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}
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inline void sdhci_msm_ice_cfg_reset(struct sdhci_host *host, u32 slot)
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{
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}
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inline int sdhci_msm_ice_cfg(struct sdhci_host *host,
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struct mmc_request *mrq, u32 slot)
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{
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return 0;
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}
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inline int sdhci_msm_ice_reset(struct sdhci_host *host)
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{
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return 0;
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}
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inline int sdhci_msm_ice_resume(struct sdhci_host *host)
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{
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return 0;
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}
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inline int sdhci_msm_ice_suspend(struct sdhci_host *host)
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{
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return 0;
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}
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inline int sdhci_msm_ice_get_status(struct sdhci_host *host,
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int *ice_status)
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{
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return 0;
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}
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inline void sdhci_msm_ice_print_regs(struct sdhci_host *host)
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{
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return;
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}
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#endif /* CONFIG_MMC_SDHCI_MSM_ICE */
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#endif /* __SDHCI_MSM_ICE_H__ */
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