Shawn Lin 48337eb7a9 clk: rockchip: Prevent calculating mmc phase if clock rate is zero ... [ Upstream commit 4bf59902b50012b1dddeeaa23b217d9c4956cdda ] The MMC sample and drv clock for rockchip platforms are derived from the bus clock output to the MMC/SDIO card. So it should never happens that the clk rate is zero given it should inherits the clock rate from its parent. If something goes wrong and makes the clock rate to be zero, the calculation would be wrong but may still make the mmc tuning process work luckily. However it makes people harder to debug when the following data transfer is unstable. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Sasha Levin <alexander.levin@microsoft.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2018-05-30 07:49:14 +02:00
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clk-cpu.c	clk: rockchip: Properly include clk.h	2015-07-20 11:11:10 -07:00
clk-inverter.c	clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)	2015-08-24 16:49:12 -07:00
clk-mmc-phase.c	clk: rockchip: Prevent calculating mmc phase if clock rate is zero	2018-05-30 07:49:14 +02:00
clk-pll.c	clk: rockchip: don't use clk_ APIs in the pll init-callback	2015-10-01 14:58:28 -07:00
clk-rk3188.c	clk: rockchip: add hclk_cpubus to the list of rk3188 critical clocks	2016-04-12 09:09:02 -07:00
clk-rk3288.c	This is the bulk of pin control changes for the v4.3 development	2015-09-04 10:22:09 -07:00
clk-rk3368.c	clk: rockchip: rk3368: fix hdmi_cec gate-register	2016-04-12 09:09:02 -07:00
clk-rockchip.c
clk.c	clk: rockchip: free memory in error cases when registering clock branches	2016-05-11 11:21:12 +02:00
clk.h	clk: rockchip: Fix PLL bandwidth	2015-07-28 11:59:12 -07:00
Makefile	clk: rockchip: add rk3368 clock controller	2015-07-06 15:09:22 -07:00
softrst.c	clk: rockchip: add reset controller	2014-07-13 12:17:07 -07:00