Sonika Jindal 474d1ec4a3 drm/i915/skl: Enabling PSR2 SU with frame sync ... We make use of HW tracking for Selective update region and enable frame sync on sink. We use hardware's hardcoded data values for frame sync and GTC. v2: Add 3200x2000 resolution restriction with PSR2, move psr2_support to i915_psr struct, add aux_frame_sync to independently control aux frame sync, rename the TP2 TIME macro for 2500us (Rodrigo, Siva) v3: Moving the resolution restriction to intel_psr_enable so that we check it only once(Durga) Cc: Durgadoss R <durgadoss.r@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com> Reviewed-by: Durgadoss R <durgadoss.r@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>		2015-04-07 10:06:38 +02:00
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drm	drm/i915/skl: Enabling PSR2 SU with frame sync	2015-04-07 10:06:38 +02:00
host1x	gpu: host1x: Provide a proper struct bus_type	2015-01-27 10:09:14 +01:00
ipu-v3	gpu: ipu-v3: do not divide by zero if the pixel clock is too large	2015-02-23 17:18:59 +01:00
vga
Makefile	gpu: host1x: Provide a proper struct bus_type	2015-01-27 10:09:14 +01:00