5be0ba2900
commit 543852af8e5902aee8f7c72c89e1513663e0f696 upstream. SARADC controller needs to be reset before programming it, otherwise it will not function properly. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Cc: Jonathan Cameron <jic23@kernel.org> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Rob Herring <robh+dt@kernel.org> Cc: linux-iio@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Tested-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Jonathan Cameron <jic23@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
31 lines
1.2 KiB
Text
31 lines
1.2 KiB
Text
Rockchip Successive Approximation Register (SAR) A/D Converter bindings
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Required properties:
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- compatible: Should be "rockchip,saradc" or "rockchip,rk3066-tsadc"
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- reg: physical base address of the controller and length of memory mapped
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region.
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- interrupts: The interrupt number to the cpu. The interrupt specifier format
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depends on the interrupt controller.
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- clocks: Must contain an entry for each entry in clock-names.
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- clock-names: Shall be "saradc" for the converter-clock, and "apb_pclk" for
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the peripheral clock.
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- vref-supply: The regulator supply ADC reference voltage.
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- #io-channel-cells: Should be 1, see ../iio-bindings.txt
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Optional properties:
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- resets: Must contain an entry for each entry in reset-names if need support
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this option. See ../reset/reset.txt for details.
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- reset-names: Must include the name "saradc-apb".
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Example:
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saradc: saradc@2006c000 {
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compatible = "rockchip,saradc";
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reg = <0x2006c000 0x100>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
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clock-names = "saradc", "apb_pclk";
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resets = <&cru SRST_SARADC>;
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reset-names = "saradc-apb";
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#io-channel-cells = <1>;
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vref-supply = <&vcc18>;
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};
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