63d32e3560
commit 02ba38a5b6d6e0bc89c7b74651f1873055028a56 upstream.
pxa_timer wants to be able to call clk_enable() etc on this clock,
but our clk_enable() implementation expects non-NULL enable/disable
operations. Provide these dummy implementations.
Unable to handle kernel NULL pointer dereference at virtual address 00000000
pgd = c0204000
[00000000] *pgd=00000000
Internal error: Oops: 80000005 [#1] ARM
Modules linked in:
CPU: 0 PID: 0 Comm: swapper Not tainted 4.8.0-rc2+ #887
Hardware name: Intel-Assabet
task: c0644590 task.stack: c0640000
PC is at 0x0
LR is at clk_enable+0x40/0x58
pc : [<00000000>] lr : [<c021b178>] psr: 600000d3
sp : c0641f60 ip : c0641f4c fp : c0641f74
r10: c1ffc7a0 r9 : 6901b118 r8 : 00000001
r7 : c0639a34 r6 : 0000001b r5 : a00000d3 r4 : c0645d70
r3 : c0645d78 r2 : 00000001 r1 : c0641ef0 r0 : c0645d70
Flags: nZCv IRQs off FIQs off Mode SVC_32 ISA ARM Segment none
Control: c020717f Table: c020717f DAC: 00000053
Process swapper (pid: 0, stack limit = 0xc0640188)
Stack: (0xc0641f60 to 0xc0642000)
1f60: 00384000 c08762e4 c0641f98 c0641f78 c063308c c021b144 00000000 00000000
1f80: 00000000 c0660b20 ffffffff c0641fa8 c0641f9c c06220ec c0633058 c0641fb8
1fa0: c0641fac c061f114 c06220dc c0641ff4 c0641fbc c061bb68 c061f0fc ffffffff
1fc0: ffffffff 00000000 c061b6cc c0639a34 c0660cd4 c0642038 c0639a30 c0645434
1fe0: c0204000 c06380f8 00000000 c0641ff8 c0208048 c061b954 00000000 00000000
Backtrace:
[<c021b138>] (clk_enable) from [<c063308c>] (pxa_timer_nodt_init+0x40/0x120)
r5:c08762e4 r4:00384000
[<c063304c>] (pxa_timer_nodt_init) from [<c06220ec>] (sa1100_timer_init+0x1c/0x20)
r6:ffffffff r5:c0660b20 r4:00000000
[<c06220d0>] (sa1100_timer_init) from [<c061f114>] (time_init+0x24/0x2c)
[<c061f0f0>] (time_init) from [<c061bb68>] (start_kernel+0x220/0x42c)
[<c061b948>] (start_kernel) from [<c0208048>] (0xc0208048)
r10:c06380f8 r8:c0204000 r7:c0645434 r6:c0639a30 r5:c0642038 r4:c0660cd4
Code: bad PC value
---[ end trace 0000000000000000 ]---
Kernel panic - not syncing: Attempted to kill the idle task!
Fixes: ee3a4020f7 ("ARM: 8250/1: sa1100: provide OSTIMER0 clock for pxa_timer")
Acked-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
149 lines
3 KiB
C
149 lines
3 KiB
C
/*
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* linux/arch/arm/mach-sa1100/clock.c
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/device.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/string.h>
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#include <linux/clk.h>
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#include <linux/spinlock.h>
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#include <linux/mutex.h>
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#include <linux/io.h>
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#include <linux/clkdev.h>
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#include <mach/hardware.h>
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#include <mach/generic.h>
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struct clkops {
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void (*enable)(struct clk *);
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void (*disable)(struct clk *);
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unsigned long (*get_rate)(struct clk *);
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};
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struct clk {
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const struct clkops *ops;
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unsigned int enabled;
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};
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#define DEFINE_CLK(_name, _ops) \
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struct clk clk_##_name = { \
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.ops = _ops, \
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}
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static DEFINE_SPINLOCK(clocks_lock);
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static void clk_gpio27_enable(struct clk *clk)
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{
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/*
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* First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111:
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* (SA-1110 Developer's Manual, section 9.1.2.1)
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*/
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GAFR |= GPIO_32_768kHz;
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GPDR |= GPIO_32_768kHz;
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TUCR = TUCR_3_6864MHz;
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}
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static void clk_gpio27_disable(struct clk *clk)
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{
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TUCR = 0;
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GPDR &= ~GPIO_32_768kHz;
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GAFR &= ~GPIO_32_768kHz;
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}
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static void clk_cpu_enable(struct clk *clk)
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{
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}
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static void clk_cpu_disable(struct clk *clk)
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{
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}
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static unsigned long clk_cpu_get_rate(struct clk *clk)
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{
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return sa11x0_getspeed(0) * 1000;
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}
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int clk_enable(struct clk *clk)
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{
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unsigned long flags;
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if (clk) {
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spin_lock_irqsave(&clocks_lock, flags);
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if (clk->enabled++ == 0)
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clk->ops->enable(clk);
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spin_unlock_irqrestore(&clocks_lock, flags);
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}
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return 0;
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}
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EXPORT_SYMBOL(clk_enable);
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void clk_disable(struct clk *clk)
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{
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unsigned long flags;
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if (clk) {
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WARN_ON(clk->enabled == 0);
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spin_lock_irqsave(&clocks_lock, flags);
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if (--clk->enabled == 0)
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clk->ops->disable(clk);
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spin_unlock_irqrestore(&clocks_lock, flags);
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}
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}
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EXPORT_SYMBOL(clk_disable);
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unsigned long clk_get_rate(struct clk *clk)
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{
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if (clk && clk->ops && clk->ops->get_rate)
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return clk->ops->get_rate(clk);
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return 0;
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}
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EXPORT_SYMBOL(clk_get_rate);
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const struct clkops clk_gpio27_ops = {
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.enable = clk_gpio27_enable,
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.disable = clk_gpio27_disable,
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};
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const struct clkops clk_cpu_ops = {
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.enable = clk_cpu_enable,
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.disable = clk_cpu_disable,
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.get_rate = clk_cpu_get_rate,
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};
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static DEFINE_CLK(gpio27, &clk_gpio27_ops);
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static DEFINE_CLK(cpu, &clk_cpu_ops);
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static unsigned long clk_36864_get_rate(struct clk *clk)
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{
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return 3686400;
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}
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static struct clkops clk_36864_ops = {
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.enable = clk_cpu_enable,
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.disable = clk_cpu_disable,
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.get_rate = clk_36864_get_rate,
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};
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static DEFINE_CLK(36864, &clk_36864_ops);
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static struct clk_lookup sa11xx_clkregs[] = {
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CLKDEV_INIT("sa1111.0", NULL, &clk_gpio27),
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CLKDEV_INIT("sa1100-rtc", NULL, NULL),
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CLKDEV_INIT("sa11x0-fb", NULL, &clk_cpu),
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CLKDEV_INIT("sa11x0-pcmcia", NULL, &clk_cpu),
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/* sa1111 names devices using internal offsets, PCMCIA is at 0x1800 */
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CLKDEV_INIT("1800", NULL, &clk_cpu),
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CLKDEV_INIT(NULL, "OSTIMER0", &clk_36864),
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};
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int __init sa11xx_clk_init(void)
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{
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clkdev_add_table(sa11xx_clkregs, ARRAY_SIZE(sa11xx_clkregs));
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return 0;
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}
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