220d9122e8
Provide functions ack_c0_eirr(), set_c0_eimr(), clear_c0_eimr() and read_c0_eirr_and_eimr() that do the EIMR and EIRR operations and update the interrupt handling code to use these functions. Also, use the EIMR register functions to mask interrupts in the irq code. The 64-bit interrupt request and mask registers (EIRR and EIMR) are accessed when the interrupts are off, and the common operations are to set or clear a bit in these registers. Using the 64-bit c0 access functions for these operations is not optimal in 32-bit, because it will disable/restore interrupts and split/join the 64-bit value during each register access. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4790/ Signed-off-by: John Crispin <blogic@openwrt.org>
297 lines
8 KiB
C
297 lines
8 KiB
C
/*
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* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
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* reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the NetLogic
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* license below:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ASM_NLM_MIPS_EXTS_H
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#define _ASM_NLM_MIPS_EXTS_H
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/*
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* XLR and XLP interrupt request and interrupt mask registers
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*/
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#define read_c0_eirr() __read_64bit_c0_register($9, 6)
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#define read_c0_eimr() __read_64bit_c0_register($9, 7)
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#define write_c0_eirr(val) __write_64bit_c0_register($9, 6, val)
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/*
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* Writing EIMR in 32 bit is a special case, the lower 8 bit of the
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* EIMR is shadowed in the status register, so we cannot save and
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* restore status register for split read.
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*/
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#define write_c0_eimr(val) \
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do { \
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if (sizeof(unsigned long) == 4) { \
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unsigned long __flags; \
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\
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local_irq_save(__flags); \
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__asm__ __volatile__( \
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".set\tmips64\n\t" \
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"dsll\t%L0, %L0, 32\n\t" \
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"dsrl\t%L0, %L0, 32\n\t" \
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"dsll\t%M0, %M0, 32\n\t" \
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"or\t%L0, %L0, %M0\n\t" \
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"dmtc0\t%L0, $9, 7\n\t" \
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".set\tmips0" \
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: : "r" (val)); \
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__flags = (__flags & 0xffff00ff) | (((val) & 0xff) << 8);\
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local_irq_restore(__flags); \
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} else \
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__write_64bit_c0_register($9, 7, (val)); \
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} while (0)
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/*
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* Handling the 64 bit EIMR and EIRR registers in 32-bit mode with
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* standard functions will be very inefficient. This provides
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* optimized functions for the normal operations on the registers.
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*
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* Call with interrupts disabled.
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*/
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static inline void ack_c0_eirr(int irq)
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{
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__asm__ __volatile__(
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".set push\n\t"
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".set mips64\n\t"
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".set noat\n\t"
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"li $1, 1\n\t"
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"dsllv $1, $1, %0\n\t"
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"dmtc0 $1, $9, 6\n\t"
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".set pop"
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: : "r" (irq));
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}
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static inline void set_c0_eimr(int irq)
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{
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__asm__ __volatile__(
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".set push\n\t"
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".set mips64\n\t"
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".set noat\n\t"
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"li $1, 1\n\t"
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"dsllv %0, $1, %0\n\t"
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"dmfc0 $1, $9, 7\n\t"
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"or $1, %0\n\t"
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"dmtc0 $1, $9, 7\n\t"
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".set pop"
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: "+r" (irq));
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}
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static inline void clear_c0_eimr(int irq)
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{
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__asm__ __volatile__(
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".set push\n\t"
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".set mips64\n\t"
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".set noat\n\t"
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"li $1, 1\n\t"
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"dsllv %0, $1, %0\n\t"
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"dmfc0 $1, $9, 7\n\t"
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"or $1, %0\n\t"
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"xor $1, %0\n\t"
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"dmtc0 $1, $9, 7\n\t"
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".set pop"
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: "+r" (irq));
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}
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/*
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* Read c0 eimr and c0 eirr, do AND of the two values, the result is
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* the interrupts which are raised and are not masked.
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*/
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static inline uint64_t read_c0_eirr_and_eimr(void)
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{
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uint64_t val;
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#ifdef CONFIG_64BIT
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val = read_c0_eimr() & read_c0_eirr();
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#else
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__asm__ __volatile__(
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".set push\n\t"
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".set mips64\n\t"
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".set noat\n\t"
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"dmfc0 %M0, $9, 6\n\t"
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"dmfc0 %L0, $9, 7\n\t"
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"and %M0, %L0\n\t"
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"dsll %L0, %M0, 32\n\t"
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"dsra %M0, %M0, 32\n\t"
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"dsra %L0, %L0, 32\n\t"
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".set pop"
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: "=r" (val));
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#endif
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return val;
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}
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static inline int hard_smp_processor_id(void)
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{
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return __read_32bit_c0_register($15, 1) & 0x3ff;
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}
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static inline int nlm_nodeid(void)
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{
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return (__read_32bit_c0_register($15, 1) >> 5) & 0x3;
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}
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static inline unsigned int nlm_core_id(void)
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{
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return (read_c0_ebase() & 0x1c) >> 2;
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}
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static inline unsigned int nlm_thread_id(void)
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{
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return read_c0_ebase() & 0x3;
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}
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#define __read_64bit_c2_split(source, sel) \
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({ \
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unsigned long long __val; \
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unsigned long __flags; \
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\
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local_irq_save(__flags); \
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if (sel == 0) \
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__asm__ __volatile__( \
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".set\tmips64\n\t" \
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"dmfc2\t%M0, " #source "\n\t" \
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"dsll\t%L0, %M0, 32\n\t" \
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"dsra\t%M0, %M0, 32\n\t" \
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"dsra\t%L0, %L0, 32\n\t" \
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".set\tmips0\n\t" \
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: "=r" (__val)); \
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else \
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__asm__ __volatile__( \
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".set\tmips64\n\t" \
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"dmfc2\t%M0, " #source ", " #sel "\n\t" \
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"dsll\t%L0, %M0, 32\n\t" \
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"dsra\t%M0, %M0, 32\n\t" \
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"dsra\t%L0, %L0, 32\n\t" \
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".set\tmips0\n\t" \
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: "=r" (__val)); \
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local_irq_restore(__flags); \
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\
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__val; \
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})
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#define __write_64bit_c2_split(source, sel, val) \
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do { \
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unsigned long __flags; \
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\
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local_irq_save(__flags); \
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if (sel == 0) \
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__asm__ __volatile__( \
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".set\tmips64\n\t" \
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"dsll\t%L0, %L0, 32\n\t" \
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"dsrl\t%L0, %L0, 32\n\t" \
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"dsll\t%M0, %M0, 32\n\t" \
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"or\t%L0, %L0, %M0\n\t" \
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"dmtc2\t%L0, " #source "\n\t" \
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".set\tmips0\n\t" \
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: : "r" (val)); \
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else \
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__asm__ __volatile__( \
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".set\tmips64\n\t" \
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"dsll\t%L0, %L0, 32\n\t" \
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"dsrl\t%L0, %L0, 32\n\t" \
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"dsll\t%M0, %M0, 32\n\t" \
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"or\t%L0, %L0, %M0\n\t" \
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"dmtc2\t%L0, " #source ", " #sel "\n\t" \
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".set\tmips0\n\t" \
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: : "r" (val)); \
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local_irq_restore(__flags); \
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} while (0)
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#define __read_32bit_c2_register(source, sel) \
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({ uint32_t __res; \
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if (sel == 0) \
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__asm__ __volatile__( \
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".set\tmips32\n\t" \
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"mfc2\t%0, " #source "\n\t" \
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".set\tmips0\n\t" \
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: "=r" (__res)); \
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else \
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__asm__ __volatile__( \
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".set\tmips32\n\t" \
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"mfc2\t%0, " #source ", " #sel "\n\t" \
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".set\tmips0\n\t" \
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: "=r" (__res)); \
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__res; \
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})
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#define __read_64bit_c2_register(source, sel) \
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({ unsigned long long __res; \
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if (sizeof(unsigned long) == 4) \
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__res = __read_64bit_c2_split(source, sel); \
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else if (sel == 0) \
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__asm__ __volatile__( \
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".set\tmips64\n\t" \
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"dmfc2\t%0, " #source "\n\t" \
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".set\tmips0\n\t" \
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: "=r" (__res)); \
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else \
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__asm__ __volatile__( \
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".set\tmips64\n\t" \
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"dmfc2\t%0, " #source ", " #sel "\n\t" \
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".set\tmips0\n\t" \
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: "=r" (__res)); \
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__res; \
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})
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#define __write_64bit_c2_register(register, sel, value) \
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do { \
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if (sizeof(unsigned long) == 4) \
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__write_64bit_c2_split(register, sel, value); \
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else if (sel == 0) \
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__asm__ __volatile__( \
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".set\tmips64\n\t" \
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"dmtc2\t%z0, " #register "\n\t" \
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".set\tmips0\n\t" \
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: : "Jr" (value)); \
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else \
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__asm__ __volatile__( \
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".set\tmips64\n\t" \
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"dmtc2\t%z0, " #register ", " #sel "\n\t" \
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".set\tmips0\n\t" \
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: : "Jr" (value)); \
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} while (0)
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#define __write_32bit_c2_register(reg, sel, value) \
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({ \
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if (sel == 0) \
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__asm__ __volatile__( \
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".set\tmips32\n\t" \
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"mtc2\t%z0, " #reg "\n\t" \
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".set\tmips0\n\t" \
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: : "Jr" (value)); \
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else \
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__asm__ __volatile__( \
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".set\tmips32\n\t" \
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"mtc2\t%z0, " #reg ", " #sel "\n\t" \
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".set\tmips0\n\t" \
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: : "Jr" (value)); \
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})
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#endif /*_ASM_NLM_MIPS_EXTS_H */
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